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wdenk42d1f032003-10-15 23:53:47 +00001/*
Andy Fleming1ced1212008-02-06 01:19:40 -06002 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Andy Fleming75b9d4a2008-08-31 16:33:26 -050028#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000029#include <common.h>
30#include <watchdog.h>
31#include <command.h>
Andy Fleming75b9d4a2008-08-31 16:33:26 -050032#include <tsec.h>
wdenk42d1f032003-10-15 23:53:47 +000033#include <asm/cache.h>
Sergei Poselenov740280e2008-06-06 15:42:40 +020034#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000035
James Yang591933c2008-02-08 16:44:53 -060036DECLARE_GLOBAL_DATA_PTR;
37
Andy Fleming1ced1212008-02-06 01:19:40 -060038struct cpu_type cpu_type_list [] = {
Kumar Gala4dbdb762008-06-10 16:53:46 -050039 CPU_TYPE_ENTRY(8533, 8533),
40 CPU_TYPE_ENTRY(8533, 8533_E),
Kumar Galaef50d6c2008-08-12 11:14:19 -050041 CPU_TYPE_ENTRY(8536, 8536),
42 CPU_TYPE_ENTRY(8536, 8536_E),
Kumar Gala4dbdb762008-06-10 16:53:46 -050043 CPU_TYPE_ENTRY(8540, 8540),
44 CPU_TYPE_ENTRY(8541, 8541),
45 CPU_TYPE_ENTRY(8541, 8541_E),
46 CPU_TYPE_ENTRY(8543, 8543),
47 CPU_TYPE_ENTRY(8543, 8543_E),
48 CPU_TYPE_ENTRY(8544, 8544),
49 CPU_TYPE_ENTRY(8544, 8544_E),
50 CPU_TYPE_ENTRY(8545, 8545),
51 CPU_TYPE_ENTRY(8545, 8545_E),
52 CPU_TYPE_ENTRY(8547, 8547_E),
53 CPU_TYPE_ENTRY(8548, 8548),
54 CPU_TYPE_ENTRY(8548, 8548_E),
55 CPU_TYPE_ENTRY(8555, 8555),
56 CPU_TYPE_ENTRY(8555, 8555_E),
57 CPU_TYPE_ENTRY(8560, 8560),
58 CPU_TYPE_ENTRY(8567, 8567),
59 CPU_TYPE_ENTRY(8567, 8567_E),
60 CPU_TYPE_ENTRY(8568, 8568),
61 CPU_TYPE_ENTRY(8568, 8568_E),
62 CPU_TYPE_ENTRY(8572, 8572),
63 CPU_TYPE_ENTRY(8572, 8572_E),
Andy Fleming1ced1212008-02-06 01:19:40 -060064};
65
Anatolij Gustschin96026d42008-06-12 12:40:11 +020066struct cpu_type *identify_cpu(u32 ver)
Kumar Gala4dbdb762008-06-10 16:53:46 -050067{
68 int i;
69 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
70 if (cpu_type_list[i].soc_ver == ver)
71 return &cpu_type_list[i];
72
73 return NULL;
74}
75
wdenk42d1f032003-10-15 23:53:47 +000076int checkcpu (void)
77{
wdenk97d80fc2004-06-09 00:34:46 +000078 sys_info_t sysinfo;
79 uint lcrr; /* local bus clock ratio register */
80 uint clkdiv; /* clock divider portion of lcrr */
81 uint pvr, svr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050082 uint fam;
wdenk97d80fc2004-06-09 00:34:46 +000083 uint ver;
84 uint major, minor;
Kumar Gala4dbdb762008-06-10 16:53:46 -050085 struct cpu_type *cpu;
Kumar Galaee1e35b2008-05-29 01:21:24 -050086#ifdef CONFIG_DDR_CLK_FREQ
Kumar Galad4357932007-12-07 04:59:26 -060087 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Kumar Galaee1e35b2008-05-29 01:21:24 -050088 u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
89#else
90 u32 ddr_ratio = 0;
91#endif
wdenk42d1f032003-10-15 23:53:47 +000092
wdenk97d80fc2004-06-09 00:34:46 +000093 svr = get_svr();
Andy Fleming1ced1212008-02-06 01:19:40 -060094 ver = SVR_SOC_VER(svr);
wdenk97d80fc2004-06-09 00:34:46 +000095 major = SVR_MAJ(svr);
Kumar Galaef50d6c2008-08-12 11:14:19 -050096#ifdef CONFIG_MPC8536
97 major &= 0x7; /* the msb of this nibble is a mfg code */
98#endif
wdenk97d80fc2004-06-09 00:34:46 +000099 minor = SVR_MIN(svr);
100
wdenk6c9e7892005-03-15 22:56:53 +0000101 puts("CPU: ");
Andy Fleming1ced1212008-02-06 01:19:40 -0600102
Kumar Gala4dbdb762008-06-10 16:53:46 -0500103 cpu = identify_cpu(ver);
104 if (cpu) {
105 puts(cpu->name);
Andy Fleming1ced1212008-02-06 01:19:40 -0600106
Kim Phillips06b41862008-06-17 17:45:22 -0500107 if (IS_E_PROCESSOR(svr))
Kumar Gala4dbdb762008-06-10 16:53:46 -0500108 puts("E");
109 } else {
wdenk97d80fc2004-06-09 00:34:46 +0000110 puts("Unknown");
Kumar Gala4dbdb762008-06-10 16:53:46 -0500111 }
Andy Fleming1ced1212008-02-06 01:19:40 -0600112
wdenk97d80fc2004-06-09 00:34:46 +0000113 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +0000114
wdenk6c9e7892005-03-15 22:56:53 +0000115 pvr = get_pvr();
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500116 fam = PVR_FAM(pvr);
wdenk6c9e7892005-03-15 22:56:53 +0000117 ver = PVR_VER(pvr);
118 major = PVR_MAJ(pvr);
119 minor = PVR_MIN(pvr);
120
121 printf("Core: ");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500122 switch (fam) {
123 case PVR_FAM(PVR_85xx):
wdenk6c9e7892005-03-15 22:56:53 +0000124 puts("E500");
125 break;
126 default:
127 puts("Unknown");
128 break;
129 }
130 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
131
wdenk97d80fc2004-06-09 00:34:46 +0000132 get_sys_info(&sysinfo);
133
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500134 puts("Clock Configuration:\n");
Kumar Gala022f1212008-04-21 09:28:36 -0500135 printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
136 printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
Kumar Galaee1e35b2008-05-29 01:21:24 -0500137
Kumar Galad4357932007-12-07 04:59:26 -0600138 switch (ddr_ratio) {
139 case 0x0:
James Yange9ea6792008-02-08 16:46:27 -0600140 printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
Kumar Gala022f1212008-04-21 09:28:36 -0500141 DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
Kumar Galad4357932007-12-07 04:59:26 -0600142 break;
143 case 0x7:
James Yange9ea6792008-02-08 16:46:27 -0600144 printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
Kumar Gala022f1212008-04-21 09:28:36 -0500145 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
Kumar Galad4357932007-12-07 04:59:26 -0600146 break;
147 default:
James Yange9ea6792008-02-08 16:46:27 -0600148 printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
Kumar Gala022f1212008-04-21 09:28:36 -0500149 DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
Kumar Galad4357932007-12-07 04:59:26 -0600150 break;
151 }
wdenk97d80fc2004-06-09 00:34:46 +0000152
153#if defined(CFG_LBC_LCRR)
154 lcrr = CFG_LBC_LCRR;
155#else
156 {
Kumar Gala04db4002007-11-29 02:10:09 -0600157 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
wdenk97d80fc2004-06-09 00:34:46 +0000158
159 lcrr = lbc->lcrr;
160 }
161#endif
162 clkdiv = lcrr & 0x0f;
163 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
Kumar Galaef50d6c2008-08-12 11:14:19 -0500164#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
165 defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500166 /*
167 * Yes, the entire PQ38 family use the same
168 * bit-representation for twice the clock divider values.
169 */
170 clkdiv *= 2;
171#endif
wdenk97d80fc2004-06-09 00:34:46 +0000172 printf("LBC:%4lu MHz\n",
Kumar Gala022f1212008-04-21 09:28:36 -0500173 DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
wdenk97d80fc2004-06-09 00:34:46 +0000174 } else {
wdenk6c9e7892005-03-15 22:56:53 +0000175 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
wdenk97d80fc2004-06-09 00:34:46 +0000176 }
177
Andy Fleming1ced1212008-02-06 01:19:40 -0600178#ifdef CONFIG_CPM2
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200179 printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
Andy Fleming1ced1212008-02-06 01:19:40 -0600180#endif
wdenk97d80fc2004-06-09 00:34:46 +0000181
wdenk6c9e7892005-03-15 22:56:53 +0000182 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000183
184 return 0;
185}
186
187
188/* ------------------------------------------------------------------------- */
189
190int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
191{
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800192 uint pvr;
193 uint ver;
Sergei Poselenov793670c2008-05-08 14:17:08 +0200194 unsigned long val, msr;
195
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800196 pvr = get_pvr();
197 ver = PVR_VER(pvr);
Sergei Poselenov793670c2008-05-08 14:17:08 +0200198
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800199 if (ver & 1){
200 /* e500 v2 core has reset control register */
201 volatile unsigned int * rstcr;
202 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
Wolfgang Denk2f152782007-05-05 18:23:11 +0200203 *rstcr = 0x2; /* HRESET_REQ */
Sergei Poselenov793670c2008-05-08 14:17:08 +0200204 udelay(100);
205 }
206
wdenk42d1f032003-10-15 23:53:47 +0000207 /*
Sergei Poselenov793670c2008-05-08 14:17:08 +0200208 * Fallthrough if the code above failed
wdenk42d1f032003-10-15 23:53:47 +0000209 * Initiate hard reset in debug control register DBCR0
210 * Make sure MSR[DE] = 1
211 */
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400212
Sergei Poselenov793670c2008-05-08 14:17:08 +0200213 msr = mfmsr ();
214 msr |= MSR_DE;
215 mtmsr (msr);
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400216
Sergei Poselenov793670c2008-05-08 14:17:08 +0200217 val = mfspr(DBCR0);
218 val |= 0x70000000;
219 mtspr(DBCR0,val);
220
wdenk42d1f032003-10-15 23:53:47 +0000221 return 1;
222}
223
224
225/*
226 * Get timebase clock frequency
227 */
228unsigned long get_tbclk (void)
229{
James Yang591933c2008-02-08 16:44:53 -0600230 return (gd->bus_clk + 4UL)/8UL;
wdenk42d1f032003-10-15 23:53:47 +0000231}
232
233
234#if defined(CONFIG_WATCHDOG)
235void
236watchdog_reset(void)
237{
238 int re_enable = disable_interrupts();
239 reset_85xx_watchdog();
240 if (re_enable) enable_interrupts();
241}
242
243void
244reset_85xx_watchdog(void)
245{
246 /*
247 * Clear TSR(WIS) bit by writing 1
248 */
249 unsigned long val;
Andy Fleming03b81b42007-04-23 01:44:44 -0500250 val = mfspr(SPRN_TSR);
251 val |= TSR_WIS;
252 mtspr(SPRN_TSR, val);
wdenk42d1f032003-10-15 23:53:47 +0000253}
254#endif /* CONFIG_WATCHDOG */
255
256#if defined(CONFIG_DDR_ECC)
wdenk42d1f032003-10-15 23:53:47 +0000257void dma_init(void) {
Kumar Gala04db4002007-11-29 02:10:09 -0600258 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000259
260 dma->satr0 = 0x02c40000;
261 dma->datr0 = 0x02c40000;
Andy Fleming03b81b42007-04-23 01:44:44 -0500262 dma->sr0 = 0xfffffff; /* clear any errors */
wdenk42d1f032003-10-15 23:53:47 +0000263 asm("sync; isync; msync");
264 return;
265}
266
267uint dma_check(void) {
Kumar Gala04db4002007-11-29 02:10:09 -0600268 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000269 volatile uint status = dma->sr0;
270
271 /* While the channel is busy, spin */
272 while((status & 4) == 4) {
273 status = dma->sr0;
274 }
275
Andy Fleming03b81b42007-04-23 01:44:44 -0500276 /* clear MR0[CS] channel start bit */
277 dma->mr0 &= 0x00000001;
278 asm("sync;isync;msync");
279
wdenk42d1f032003-10-15 23:53:47 +0000280 if (status != 0) {
281 printf ("DMA Error: status = %x\n", status);
282 }
283 return status;
284}
285
286int dma_xfer(void *dest, uint count, void *src) {
Kumar Gala04db4002007-11-29 02:10:09 -0600287 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000288
289 dma->dar0 = (uint) dest;
290 dma->sar0 = (uint) src;
291 dma->bcr0 = count;
292 dma->mr0 = 0xf000004;
293 asm("sync;isync;msync");
294 dma->mr0 = 0xf000005;
295 asm("sync;isync;msync");
296 return dma_check();
297}
298#endif
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500299
Sergei Poselenov740280e2008-06-06 15:42:40 +0200300/*
301 * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
302 * are hardcoded as "1"."size" is the number or entries, not a sizeof.
303 */
304void upmconfig (uint upm, uint * table, uint size)
305{
306 int i, mdr, mad, old_mad = 0;
307 volatile u32 *mxmr;
308 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
309 int loopval = 0x00004440;
310 volatile u32 *brp,*orp;
311 volatile u8* dummy = NULL;
312 int upmmask;
313
314 switch (upm) {
315 case UPMA:
316 mxmr = &lbc->mamr;
317 upmmask = BR_MS_UPMA;
318 break;
319 case UPMB:
320 mxmr = &lbc->mbmr;
321 upmmask = BR_MS_UPMB;
322 break;
323 case UPMC:
324 mxmr = &lbc->mcmr;
325 upmmask = BR_MS_UPMC;
326 break;
327 default:
328 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
329 hang();
330 }
331
332 /* Find the address for the dummy write transaction */
333 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
334 i++, brp += 2, orp += 2) {
Wolfgang Denke093a242008-06-28 23:34:37 +0200335
Sergei Poselenov740280e2008-06-06 15:42:40 +0200336 /* Look for a valid BR with selected UPM */
337 if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
338 dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
339 break;
340 }
341 }
342
343 if (i == 8) {
344 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
345 hang();
346 }
347
348 for (i = 0; i < size; i++) {
349 /* 1 */
350 out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
351 /* 2 */
352 out_be32(&lbc->mdr, table[i]);
353 /* 3 */
354 mdr = in_be32(&lbc->mdr);
355 /* 4 */
356 *(volatile u8 *)dummy = 0;
357 /* 5 */
358 do {
359 mad = in_be32(mxmr) & 0x3f;
360 } while (mad <= old_mad && !(!mad && i == (size-1)));
361 old_mad = mad;
362 }
363 out_be32(mxmr, loopval); /* OP_NORMAL */
364}
Ben Warrendd354792008-06-23 22:57:27 -0700365
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500366
367/*
368 * Initializes on-chip ethernet controllers.
369 * to override, implement board_eth_init()
Ben Warrendd354792008-06-23 22:57:27 -0700370 */
Ben Warrendd354792008-06-23 22:57:27 -0700371int cpu_eth_init(bd_t *bis)
372{
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500373#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC)
374 tsec_standard_init(bis);
Ben Warrendd354792008-06-23 22:57:27 -0700375#endif
Andy Fleming75b9d4a2008-08-31 16:33:26 -0500376
Ben Warrendd354792008-06-23 22:57:27 -0700377 return 0;
378}