Tom Rini | 278b90c | 2018-02-03 12:10:38 -0500 | [diff] [blame] | 1 | CONFIG_SYS_TEXT_BASE=0 |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 2 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
Tom Rini | fa2c146 | 2018-02-10 16:54:38 -0500 | [diff] [blame] | 3 | CONFIG_DISTRO_DEFAULTS=y |
Tom Rini | 86cf1c8 | 2018-08-16 08:16:24 -0400 | [diff] [blame] | 4 | CONFIG_NR_DRAM_BANKS=1 |
Tom Rini | 48f6232 | 2017-08-25 17:50:27 -0400 | [diff] [blame] | 5 | CONFIG_ANDROID_BOOT_IMAGE=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 6 | CONFIG_FIT=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 7 | CONFIG_FIT_SIGNATURE=y |
Jagan Teki | 3788b45 | 2017-01-21 11:48:33 +0100 | [diff] [blame] | 8 | CONFIG_FIT_VERBOSE=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 9 | CONFIG_BOOTSTAGE=y |
| 10 | CONFIG_BOOTSTAGE_REPORT=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 11 | CONFIG_BOOTSTAGE_FDT=y |
| 12 | CONFIG_BOOTSTAGE_STASH=y |
| 13 | CONFIG_BOOTSTAGE_STASH_ADDR=0x0 |
| 14 | CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 |
Tom Rini | fa2c146 | 2018-02-10 16:54:38 -0500 | [diff] [blame] | 15 | # CONFIG_USE_BOOTCOMMAND is not set |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 16 | CONFIG_CONSOLE_RECORD=y |
| 17 | CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 |
Simon Glass | 98af879 | 2016-10-17 20:12:35 -0600 | [diff] [blame] | 18 | CONFIG_SILENT_CONSOLE=y |
Mario Six | 78eba69 | 2018-03-28 14:38:17 +0200 | [diff] [blame] | 19 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 20 | CONFIG_CMD_CPU=y |
| 21 | CONFIG_CMD_LICENSE=y |
| 22 | CONFIG_CMD_BOOTZ=y |
| 23 | # CONFIG_CMD_ELF is not set |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 24 | CONFIG_CMD_ASKENV=y |
| 25 | CONFIG_CMD_GREPENV=y |
Simon Glass | a55d29d | 2017-05-17 03:25:13 -0600 | [diff] [blame] | 26 | CONFIG_CMD_ENV_CALLBACK=y |
Simon Glass | ffc7658 | 2017-05-17 03:25:14 -0600 | [diff] [blame] | 27 | CONFIG_CMD_ENV_FLAGS=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 28 | CONFIG_LOOPW=y |
Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 29 | CONFIG_CMD_MD5SUM=y |
| 30 | CONFIG_CMD_MEMINFO=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 31 | CONFIG_CMD_MEMTEST=y |
| 32 | CONFIG_CMD_MX_CYCLIC=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 33 | CONFIG_CMD_DEMO=y |
Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 34 | CONFIG_CMD_GPIO=y |
Patrick Delaunay | b331cd6 | 2017-01-27 11:00:42 +0100 | [diff] [blame] | 35 | CONFIG_CMD_GPT=y |
Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 36 | CONFIG_CMD_IDE=y |
| 37 | CONFIG_CMD_I2C=y |
Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 38 | CONFIG_CMD_PCI=y |
| 39 | CONFIG_CMD_REMOTEPROC=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 40 | CONFIG_CMD_SF=y |
| 41 | CONFIG_CMD_SPI=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 42 | CONFIG_CMD_USB=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 43 | CONFIG_CMD_TFTPPUT=y |
| 44 | CONFIG_CMD_TFTPSRV=y |
| 45 | CONFIG_CMD_RARP=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 46 | CONFIG_CMD_CDP=y |
| 47 | CONFIG_CMD_SNTP=y |
| 48 | CONFIG_CMD_DNS=y |
| 49 | CONFIG_CMD_LINK_LOCAL=y |
Simon Glass | 0f71025 | 2017-04-26 22:27:55 -0600 | [diff] [blame] | 50 | CONFIG_CMD_BMP=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 51 | CONFIG_CMD_TIME=y |
| 52 | CONFIG_CMD_TIMER=y |
| 53 | CONFIG_CMD_SOUND=y |
| 54 | CONFIG_CMD_BOOTSTAGE=y |
| 55 | CONFIG_CMD_PMIC=y |
| 56 | CONFIG_CMD_REGULATOR=y |
| 57 | CONFIG_CMD_TPM=y |
| 58 | CONFIG_CMD_TPM_TEST=y |
Simon Glass | d66a10f | 2017-04-26 22:27:58 -0600 | [diff] [blame] | 59 | CONFIG_CMD_CBFS=y |
Simon Glass | 9707274 | 2017-04-26 22:28:03 -0600 | [diff] [blame] | 60 | CONFIG_CMD_CRAMFS=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 61 | CONFIG_CMD_EXT4_WRITE=y |
Patrick Delaunay | f18fa31 | 2017-01-27 11:00:36 +0100 | [diff] [blame] | 62 | CONFIG_MAC_PARTITION=y |
Patrick Delaunay | 863c5b6 | 2017-01-27 11:00:39 +0100 | [diff] [blame] | 63 | CONFIG_AMIGA_PARTITION=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 64 | CONFIG_OF_CONTROL=y |
| 65 | CONFIG_OF_HOSTFILE=y |
Tom Rini | 8c5cad0 | 2018-09-03 15:26:12 -0400 | [diff] [blame] | 66 | CONFIG_DEFAULT_DEVICE_TREE="sandbox" |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 67 | CONFIG_NETCONSOLE=y |
| 68 | CONFIG_REGMAP=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 69 | CONFIG_SYSCON=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 70 | CONFIG_DEVRES=y |
| 71 | CONFIG_DEBUG_DEVRES=y |
| 72 | CONFIG_ADC=y |
| 73 | CONFIG_ADC_SANDBOX=y |
Simon Glass | 896a74f | 2016-10-01 14:43:18 -0600 | [diff] [blame] | 74 | # CONFIG_BLK is not set |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 75 | CONFIG_CLK=y |
| 76 | CONFIG_CPU=y |
| 77 | CONFIG_DM_DEMO=y |
| 78 | CONFIG_DM_DEMO_SIMPLE=y |
| 79 | CONFIG_DM_DEMO_SHAPE=y |
| 80 | CONFIG_PM8916_GPIO=y |
| 81 | CONFIG_SANDBOX_GPIO=y |
| 82 | CONFIG_DM_I2C_COMPAT=y |
| 83 | CONFIG_I2C_CROS_EC_TUNNEL=y |
| 84 | CONFIG_I2C_CROS_EC_LDO=y |
| 85 | CONFIG_DM_I2C_GPIO=y |
| 86 | CONFIG_SYS_I2C_SANDBOX=y |
| 87 | CONFIG_I2C_MUX=y |
| 88 | CONFIG_SPL_I2C_MUX=y |
| 89 | CONFIG_I2C_ARB_GPIO_CHALLENGE=y |
| 90 | CONFIG_CROS_EC_KEYB=y |
Simon Glass | ef26d60 | 2016-10-17 20:12:37 -0600 | [diff] [blame] | 91 | CONFIG_I8042_KEYB=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 92 | CONFIG_LED=y |
Simon Glass | 53378da | 2017-04-10 11:34:57 -0600 | [diff] [blame] | 93 | CONFIG_LED_BLINK=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 94 | CONFIG_LED_GPIO=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 95 | CONFIG_CROS_EC=y |
| 96 | CONFIG_CROS_EC_I2C=y |
| 97 | CONFIG_CROS_EC_LPC=y |
| 98 | CONFIG_CROS_EC_SANDBOX=y |
| 99 | CONFIG_CROS_EC_SPI=y |
| 100 | CONFIG_PWRSEQ=y |
| 101 | CONFIG_SPL_PWRSEQ=y |
Jagan Teki | 3788b45 | 2017-01-21 11:48:33 +0100 | [diff] [blame] | 102 | # CONFIG_MMC is not set |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 103 | CONFIG_SPI_FLASH_SANDBOX=y |
| 104 | CONFIG_SPI_FLASH=y |
| 105 | CONFIG_SPI_FLASH_ATMEL=y |
| 106 | CONFIG_SPI_FLASH_EON=y |
| 107 | CONFIG_SPI_FLASH_GIGADEVICE=y |
| 108 | CONFIG_SPI_FLASH_MACRONIX=y |
| 109 | CONFIG_SPI_FLASH_SPANSION=y |
| 110 | CONFIG_SPI_FLASH_STMICRO=y |
| 111 | CONFIG_SPI_FLASH_SST=y |
| 112 | CONFIG_SPI_FLASH_WINBOND=y |
| 113 | CONFIG_DM_ETH=y |
Tom Rini | af27382 | 2016-10-26 17:15:37 -0400 | [diff] [blame] | 114 | CONFIG_PCI=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 115 | CONFIG_DM_PCI=y |
| 116 | CONFIG_DM_PCI_COMPAT=y |
| 117 | CONFIG_PCI_SANDBOX=y |
Tom Rini | fb82fe3 | 2017-06-19 09:47:40 -0400 | [diff] [blame] | 118 | CONFIG_PHY=y |
| 119 | CONFIG_PHY_SANDBOX=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 120 | CONFIG_PINCTRL=y |
| 121 | CONFIG_PINCONF=y |
Philipp Tomsich | 51c7f34 | 2017-04-19 16:46:37 +0200 | [diff] [blame] | 122 | CONFIG_PINCTRL_ROCKCHIP_RK3036=y |
| 123 | CONFIG_PINCTRL_ROCKCHIP_RK3288=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 124 | CONFIG_PINCTRL_SANDBOX=y |
| 125 | CONFIG_DM_PMIC=y |
| 126 | CONFIG_PMIC_ACT8846=y |
| 127 | CONFIG_DM_PMIC_PFUZE100=y |
| 128 | CONFIG_DM_PMIC_MAX77686=y |
| 129 | CONFIG_PMIC_PM8916=y |
Jacob Chen | 453c5a9 | 2017-05-02 14:54:52 +0800 | [diff] [blame] | 130 | CONFIG_PMIC_RK8XX=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 131 | CONFIG_PMIC_S2MPS11=y |
| 132 | CONFIG_DM_PMIC_SANDBOX=y |
| 133 | CONFIG_PMIC_S5M8767=y |
| 134 | CONFIG_PMIC_TPS65090=y |
| 135 | CONFIG_DM_REGULATOR=y |
| 136 | CONFIG_REGULATOR_ACT8846=y |
| 137 | CONFIG_DM_REGULATOR_PFUZE100=y |
| 138 | CONFIG_DM_REGULATOR_MAX77686=y |
| 139 | CONFIG_DM_REGULATOR_FIXED=y |
Jacob Chen | 453c5a9 | 2017-05-02 14:54:52 +0800 | [diff] [blame] | 140 | CONFIG_REGULATOR_RK8XX=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 141 | CONFIG_REGULATOR_S5M8767=y |
| 142 | CONFIG_DM_REGULATOR_SANDBOX=y |
| 143 | CONFIG_REGULATOR_TPS65090=y |
Tom Rini | 2681e78 | 2017-05-01 11:41:11 -0400 | [diff] [blame] | 144 | CONFIG_DM_PWM=y |
| 145 | CONFIG_PWM_SANDBOX=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 146 | CONFIG_RAM=y |
| 147 | CONFIG_REMOTEPROC_SANDBOX=y |
| 148 | CONFIG_DM_RTC=y |
| 149 | CONFIG_SANDBOX_SERIAL=y |
| 150 | CONFIG_SOUND=y |
| 151 | CONFIG_SOUND_SANDBOX=y |
| 152 | CONFIG_SANDBOX_SPI=y |
| 153 | CONFIG_SPMI=y |
| 154 | CONFIG_SPMI_SANDBOX=y |
Tom Rini | aca5cd2 | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 155 | CONFIG_SYSRESET=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 156 | CONFIG_TIMER=y |
| 157 | CONFIG_TIMER_EARLY=y |
| 158 | CONFIG_SANDBOX_TIMER=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 159 | CONFIG_USB=y |
| 160 | CONFIG_DM_USB=y |
| 161 | CONFIG_USB_EMUL=y |
| 162 | CONFIG_USB_STORAGE=y |
| 163 | CONFIG_USB_KEYBOARD=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 164 | CONFIG_DM_VIDEO=y |
| 165 | CONFIG_CONSOLE_ROTATION=y |
| 166 | CONFIG_CONSOLE_TRUETYPE=y |
| 167 | CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y |
| 168 | CONFIG_VIDEO_SANDBOX_SDL=y |
Simon Glass | deb95999 | 2017-04-26 22:27:59 -0600 | [diff] [blame] | 169 | CONFIG_FS_CBFS=y |
Simon Glass | 80e44cf | 2017-04-26 22:28:04 -0600 | [diff] [blame] | 170 | CONFIG_FS_CRAMFS=y |
Simon Glass | f960ca0 | 2016-05-01 11:35:50 -0600 | [diff] [blame] | 171 | CONFIG_CMD_DHRYSTONE=y |
| 172 | CONFIG_TPM=y |
| 173 | CONFIG_LZ4=y |
| 174 | CONFIG_ERRNO_STR=y |
| 175 | CONFIG_UNIT_TEST=y |
| 176 | CONFIG_UT_TIME=y |
| 177 | CONFIG_UT_DM=y |
| 178 | CONFIG_UT_ENV=y |