blob: 2604a687ab9f5d62bd3bb1634438635954e8c9c9 [file] [log] [blame]
Simon Glass45b5a372015-04-29 22:25:59 -06001/*
2 * Copyright (C) 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * Based on code from the coreboot file of the same name
7 */
8
9#include <common.h>
10#include <cpu.h>
11#include <dm.h>
12#include <errno.h>
13#include <malloc.h>
14#include <asm/atomic.h>
15#include <asm/cpu.h>
16#include <asm/interrupt.h>
17#include <asm/lapic.h>
Simon Glass6bcb6752016-03-11 22:07:09 -070018#include <asm/microcode.h>
Simon Glass45b5a372015-04-29 22:25:59 -060019#include <asm/mp.h>
Bin Menga2d73fd2015-06-23 12:18:50 +080020#include <asm/msr.h>
Simon Glass45b5a372015-04-29 22:25:59 -060021#include <asm/mtrr.h>
Bin Menga2d73fd2015-06-23 12:18:50 +080022#include <asm/processor.h>
Simon Glass45b5a372015-04-29 22:25:59 -060023#include <asm/sipi.h>
Miao Yande752c52016-01-07 01:32:04 -080024#include <asm/fw_cfg.h>
Simon Glass45b5a372015-04-29 22:25:59 -060025#include <dm/device-internal.h>
26#include <dm/uclass-internal.h>
Miao Yande752c52016-01-07 01:32:04 -080027#include <dm/lists.h>
28#include <dm/root.h>
Simon Glass45b5a372015-04-29 22:25:59 -060029#include <linux/linkage.h>
30
Simon Glass8b097912015-07-31 09:31:31 -060031DECLARE_GLOBAL_DATA_PTR;
32
Bin Meng6e6f4ce2015-06-17 11:15:36 +080033/* Total CPUs include BSP */
34static int num_cpus;
35
Simon Glass45b5a372015-04-29 22:25:59 -060036/* This also needs to match the sipi.S assembly code for saved MSR encoding */
37struct saved_msr {
38 uint32_t index;
39 uint32_t lo;
40 uint32_t hi;
41} __packed;
42
43
44struct mp_flight_plan {
45 int num_records;
46 struct mp_flight_record *records;
47};
48
49static struct mp_flight_plan mp_info;
50
51struct cpu_map {
52 struct udevice *dev;
53 int apic_id;
54 int err_code;
55};
56
57static inline void barrier_wait(atomic_t *b)
58{
59 while (atomic_read(b) == 0)
60 asm("pause");
61 mfence();
62}
63
64static inline void release_barrier(atomic_t *b)
65{
66 mfence();
67 atomic_set(b, 1);
68}
69
Bin Menga2d73fd2015-06-23 12:18:50 +080070static inline void stop_this_cpu(void)
71{
72 /* Called by an AP when it is ready to halt and wait for a new task */
73 for (;;)
74 cpu_hlt();
75}
76
Simon Glass45b5a372015-04-29 22:25:59 -060077/* Returns 1 if timeout waiting for APs. 0 if target APs found */
78static int wait_for_aps(atomic_t *val, int target, int total_delay,
79 int delay_step)
80{
81 int timeout = 0;
82 int delayed = 0;
83
84 while (atomic_read(val) != target) {
85 udelay(delay_step);
86 delayed += delay_step;
87 if (delayed >= total_delay) {
88 timeout = 1;
89 break;
90 }
91 }
92
93 return timeout;
94}
95
96static void ap_do_flight_plan(struct udevice *cpu)
97{
98 int i;
99
100 for (i = 0; i < mp_info.num_records; i++) {
101 struct mp_flight_record *rec = &mp_info.records[i];
102
103 atomic_inc(&rec->cpus_entered);
104 barrier_wait(&rec->barrier);
105
106 if (rec->ap_call != NULL)
107 rec->ap_call(cpu, rec->ap_arg);
108 }
109}
110
Miao Yan24fb4902016-01-07 01:32:02 -0800111static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
Simon Glass45b5a372015-04-29 22:25:59 -0600112{
113 struct udevice *dev;
114
115 *devp = NULL;
116 for (uclass_find_first_device(UCLASS_CPU, &dev);
117 dev;
118 uclass_find_next_device(&dev)) {
119 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
120
121 if (plat->cpu_id == apic_id) {
122 *devp = dev;
123 return 0;
124 }
125 }
126
127 return -ENOENT;
128}
129
130/*
131 * By the time APs call ap_init() caching has been setup, and microcode has
132 * been loaded
133 */
134static void ap_init(unsigned int cpu_index)
135{
136 struct udevice *dev;
137 int apic_id;
138 int ret;
139
140 /* Ensure the local apic is enabled */
141 enable_lapic();
142
143 apic_id = lapicid();
Miao Yan24fb4902016-01-07 01:32:02 -0800144 ret = find_cpu_by_apic_id(apic_id, &dev);
Simon Glass45b5a372015-04-29 22:25:59 -0600145 if (ret) {
146 debug("Unknown CPU apic_id %x\n", apic_id);
147 goto done;
148 }
149
150 debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
151 dev ? dev->name : "(apic_id not found)");
152
153 /* Walk the flight plan */
154 ap_do_flight_plan(dev);
155
156 /* Park the AP */
157 debug("parking\n");
158done:
159 stop_this_cpu();
160}
161
162static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
163 MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
164 MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
165 MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
166 MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
167};
168
169static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
170{
171 msr_t msr;
172
173 msr = msr_read(index);
174 entry->index = index;
175 entry->lo = msr.lo;
176 entry->hi = msr.hi;
177
178 /* Return the next entry */
179 entry++;
180 return entry;
181}
182
183static int save_bsp_msrs(char *start, int size)
184{
185 int msr_count;
186 int num_var_mtrrs;
187 struct saved_msr *msr_entry;
188 int i;
189 msr_t msr;
190
191 /* Determine number of MTRRs need to be saved */
192 msr = msr_read(MTRR_CAP_MSR);
193 num_var_mtrrs = msr.lo & 0xff;
194
195 /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
196 msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
197
198 if ((msr_count * sizeof(struct saved_msr)) > size) {
Simon Glass2254e342016-03-06 19:28:22 -0700199 printf("Cannot mirror all %d msrs\n", msr_count);
Simon Glass45b5a372015-04-29 22:25:59 -0600200 return -ENOSPC;
201 }
202
203 msr_entry = (void *)start;
204 for (i = 0; i < NUM_FIXED_MTRRS; i++)
205 msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
206
207 for (i = 0; i < num_var_mtrrs; i++) {
208 msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
209 msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
210 }
211
212 msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
213
214 return msr_count;
215}
216
Miao Yanb28cecd2016-01-07 01:32:03 -0800217static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
Simon Glass45b5a372015-04-29 22:25:59 -0600218{
219 struct sipi_params_16bit *params16;
220 struct sipi_params *params;
221 static char msr_save[512];
222 char *stack;
223 ulong addr;
224 int code_len;
225 int size;
226 int ret;
227
228 /* Copy in the code */
229 code_len = ap_start16_code_end - ap_start16;
230 debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
231 code_len);
232 memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
233
234 addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
235 params16 = (struct sipi_params_16bit *)addr;
236 params16->ap_start = (uint32_t)ap_start;
237 params16->gdt = (uint32_t)gd->arch.gdt;
238 params16->gdt_limit = X86_GDT_SIZE - 1;
239 debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
240
241 params = (struct sipi_params *)sipi_params;
242 debug("SIPI 32-bit params at %p\n", params);
243 params->idt_ptr = (uint32_t)x86_get_idt();
244
245 params->stack_size = CONFIG_AP_STACK_SIZE;
Miao Yanb28cecd2016-01-07 01:32:03 -0800246 size = params->stack_size * num_cpus;
Stephen Warren4fd64d02016-02-12 14:27:56 -0700247 stack = memalign(4096, size);
Simon Glass45b5a372015-04-29 22:25:59 -0600248 if (!stack)
249 return -ENOMEM;
250 params->stack_top = (u32)(stack + size);
Simon Glasse77b62e2016-03-11 22:07:11 -0700251#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
252 params->microcode_ptr = ucode_base;
253 debug("Microcode at %x\n", params->microcode_ptr);
254#endif
Simon Glass45b5a372015-04-29 22:25:59 -0600255 params->msr_table_ptr = (u32)msr_save;
256 ret = save_bsp_msrs(msr_save, sizeof(msr_save));
257 if (ret < 0)
258 return ret;
259 params->msr_count = ret;
260
261 params->c_handler = (uint32_t)&ap_init;
262
263 *ap_countp = &params->ap_count;
264 atomic_set(*ap_countp, 0);
265 debug("SIPI vector is ready\n");
266
267 return 0;
268}
269
270static int check_cpu_devices(int expected_cpus)
271{
272 int i;
273
274 for (i = 0; i < expected_cpus; i++) {
275 struct udevice *dev;
276 int ret;
277
278 ret = uclass_find_device(UCLASS_CPU, i, &dev);
279 if (ret) {
280 debug("Cannot find CPU %d in device tree\n", i);
281 return ret;
282 }
283 }
284
285 return 0;
286}
287
288/* Returns 1 for timeout. 0 on success */
Simon Glass2254e342016-03-06 19:28:22 -0700289static int apic_wait_timeout(int total_delay, const char *msg)
Simon Glass45b5a372015-04-29 22:25:59 -0600290{
291 int total = 0;
Simon Glass45b5a372015-04-29 22:25:59 -0600292
Simon Glass2254e342016-03-06 19:28:22 -0700293 if (!(lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY))
294 return 0;
295
296 debug("Waiting for %s...", msg);
Simon Glass45b5a372015-04-29 22:25:59 -0600297 while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
Simon Glass2254e342016-03-06 19:28:22 -0700298 udelay(50);
299 total += 50;
Simon Glass45b5a372015-04-29 22:25:59 -0600300 if (total >= total_delay) {
Simon Glass2254e342016-03-06 19:28:22 -0700301 debug("timed out: aborting\n");
302 return -ETIMEDOUT;
Simon Glass45b5a372015-04-29 22:25:59 -0600303 }
304 }
Simon Glass2254e342016-03-06 19:28:22 -0700305 debug("done\n");
Simon Glass45b5a372015-04-29 22:25:59 -0600306
Simon Glass2254e342016-03-06 19:28:22 -0700307 return 0;
Simon Glass45b5a372015-04-29 22:25:59 -0600308}
309
310static int start_aps(int ap_count, atomic_t *num_aps)
311{
312 int sipi_vector;
313 /* Max location is 4KiB below 1MiB */
314 const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
315
316 if (ap_count == 0)
317 return 0;
318
319 /* The vector is sent as a 4k aligned address in one byte */
320 sipi_vector = AP_DEFAULT_BASE >> 12;
321
322 if (sipi_vector > max_vector_loc) {
323 printf("SIPI vector too large! 0x%08x\n",
324 sipi_vector);
325 return -1;
326 }
327
328 debug("Attempting to start %d APs\n", ap_count);
329
Simon Glass2254e342016-03-06 19:28:22 -0700330 if (apic_wait_timeout(1000, "ICR not to be busy"))
331 return -ETIMEDOUT;
Simon Glass45b5a372015-04-29 22:25:59 -0600332
333 /* Send INIT IPI to all but self */
Bin Menga2d73fd2015-06-23 12:18:50 +0800334 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
335 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
336 LAPIC_DM_INIT);
Simon Glass2254e342016-03-06 19:28:22 -0700337 debug("Waiting for 10ms after sending INIT\n");
Simon Glass45b5a372015-04-29 22:25:59 -0600338 mdelay(10);
339
340 /* Send 1st SIPI */
Simon Glass2254e342016-03-06 19:28:22 -0700341 if (apic_wait_timeout(1000, "ICR not to be busy"))
342 return -ETIMEDOUT;
Simon Glass45b5a372015-04-29 22:25:59 -0600343
Bin Menga2d73fd2015-06-23 12:18:50 +0800344 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
345 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
346 LAPIC_DM_STARTUP | sipi_vector);
Simon Glass2254e342016-03-06 19:28:22 -0700347 if (apic_wait_timeout(10000, "first SIPI to complete"))
348 return -ETIMEDOUT;
Simon Glass45b5a372015-04-29 22:25:59 -0600349
350 /* Wait for CPUs to check in up to 200 us */
351 wait_for_aps(num_aps, ap_count, 200, 15);
352
353 /* Send 2nd SIPI */
Simon Glass2254e342016-03-06 19:28:22 -0700354 if (apic_wait_timeout(1000, "ICR not to be busy"))
355 return -ETIMEDOUT;
Simon Glass45b5a372015-04-29 22:25:59 -0600356
Bin Menga2d73fd2015-06-23 12:18:50 +0800357 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
358 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
359 LAPIC_DM_STARTUP | sipi_vector);
Simon Glass2254e342016-03-06 19:28:22 -0700360 if (apic_wait_timeout(10000, "second SIPI to complete"))
361 return -ETIMEDOUT;
Simon Glass45b5a372015-04-29 22:25:59 -0600362
363 /* Wait for CPUs to check in */
364 if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
Simon Glass2254e342016-03-06 19:28:22 -0700365 debug("Not all APs checked in: %d/%d\n",
Simon Glass45b5a372015-04-29 22:25:59 -0600366 atomic_read(num_aps), ap_count);
367 return -1;
368 }
369
370 return 0;
371}
372
373static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
374{
375 int i;
376 int ret = 0;
377 const int timeout_us = 100000;
378 const int step_us = 100;
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800379 int num_aps = num_cpus - 1;
Simon Glass45b5a372015-04-29 22:25:59 -0600380
381 for (i = 0; i < mp_params->num_records; i++) {
382 struct mp_flight_record *rec = &mp_params->flight_plan[i];
383
384 /* Wait for APs if the record is not released */
385 if (atomic_read(&rec->barrier) == 0) {
386 /* Wait for the APs to check in */
387 if (wait_for_aps(&rec->cpus_entered, num_aps,
388 timeout_us, step_us)) {
Simon Glass2254e342016-03-06 19:28:22 -0700389 debug("MP record %d timeout\n", i);
Simon Glass45b5a372015-04-29 22:25:59 -0600390 ret = -1;
391 }
392 }
393
394 if (rec->bsp_call != NULL)
395 rec->bsp_call(cpu, rec->bsp_arg);
396
397 release_barrier(&rec->barrier);
398 }
399 return ret;
400}
401
402static int init_bsp(struct udevice **devp)
403{
404 char processor_name[CPU_MAX_NAME_LEN];
405 int apic_id;
406 int ret;
407
408 cpu_get_name(processor_name);
Simon Glass2254e342016-03-06 19:28:22 -0700409 debug("CPU: %s\n", processor_name);
Simon Glass45b5a372015-04-29 22:25:59 -0600410
Bin Meng61788e42015-06-17 11:15:37 +0800411 lapic_setup();
Simon Glass45b5a372015-04-29 22:25:59 -0600412
413 apic_id = lapicid();
Miao Yan24fb4902016-01-07 01:32:02 -0800414 ret = find_cpu_by_apic_id(apic_id, devp);
Simon Glass45b5a372015-04-29 22:25:59 -0600415 if (ret) {
416 printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
417 return ret;
418 }
419
420 return 0;
421}
422
Miao Yande752c52016-01-07 01:32:04 -0800423#ifdef CONFIG_QEMU
424static int qemu_cpu_fixup(void)
425{
426 int ret;
427 int cpu_num;
428 int cpu_online;
429 struct udevice *dev, *pdev;
430 struct cpu_platdata *plat;
431 char *cpu;
432
433 /* first we need to find '/cpus' */
434 for (device_find_first_child(dm_root(), &pdev);
435 pdev;
436 device_find_next_child(&pdev)) {
437 if (!strcmp(pdev->name, "cpus"))
438 break;
439 }
440 if (!pdev) {
441 printf("unable to find cpus device\n");
442 return -ENODEV;
443 }
444
445 /* calculate cpus that are already bound */
446 cpu_num = 0;
447 for (uclass_find_first_device(UCLASS_CPU, &dev);
448 dev;
449 uclass_find_next_device(&dev)) {
450 cpu_num++;
451 }
452
453 /* get actual cpu number */
454 cpu_online = qemu_fwcfg_online_cpus();
455 if (cpu_online < 0) {
456 printf("unable to get online cpu number: %d\n", cpu_online);
457 return cpu_online;
458 }
459
460 /* bind addtional cpus */
461 dev = NULL;
462 for (; cpu_num < cpu_online; cpu_num++) {
463 /*
464 * allocate device name here as device_bind_driver() does
465 * not copy device name, 8 bytes are enough for
466 * sizeof("cpu@") + 3 digits cpu number + '\0'
467 */
468 cpu = malloc(8);
469 if (!cpu) {
470 printf("unable to allocate device name\n");
471 return -ENOMEM;
472 }
473 sprintf(cpu, "cpu@%d", cpu_num);
474 ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev);
475 if (ret) {
476 printf("binding cpu@%d failed: %d\n", cpu_num, ret);
477 return ret;
478 }
479 plat = dev_get_parent_platdata(dev);
480 plat->cpu_id = cpu_num;
481 }
482 return 0;
483}
484#endif
485
Simon Glass45b5a372015-04-29 22:25:59 -0600486int mp_init(struct mp_params *p)
487{
488 int num_aps;
489 atomic_t *ap_count;
490 struct udevice *cpu;
491 int ret;
492
493 /* This will cause the CPUs devices to be bound */
494 struct uclass *uc;
495 ret = uclass_get(UCLASS_CPU, &uc);
496 if (ret)
497 return ret;
498
Miao Yande752c52016-01-07 01:32:04 -0800499#ifdef CONFIG_QEMU
500 ret = qemu_cpu_fixup();
501 if (ret)
502 return ret;
503#endif
504
Simon Glass45b5a372015-04-29 22:25:59 -0600505 ret = init_bsp(&cpu);
506 if (ret) {
507 debug("Cannot init boot CPU: err=%d\n", ret);
508 return ret;
509 }
510
511 if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
512 printf("Invalid MP parameters\n");
513 return -1;
514 }
515
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800516 num_cpus = cpu_get_count(cpu);
517 if (num_cpus < 0) {
518 debug("Cannot get number of CPUs: err=%d\n", num_cpus);
519 return num_cpus;
520 }
521
522 if (num_cpus < 2)
523 debug("Warning: Only 1 CPU is detected\n");
524
525 ret = check_cpu_devices(num_cpus);
Simon Glass45b5a372015-04-29 22:25:59 -0600526 if (ret)
527 debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
528
529 /* Copy needed parameters so that APs have a reference to the plan */
530 mp_info.num_records = p->num_records;
531 mp_info.records = p->flight_plan;
532
533 /* Load the SIPI vector */
Miao Yanb28cecd2016-01-07 01:32:03 -0800534 ret = load_sipi_vector(&ap_count, num_cpus);
Simon Glass45b5a372015-04-29 22:25:59 -0600535 if (ap_count == NULL)
536 return -1;
537
538 /*
539 * Make sure SIPI data hits RAM so the APs that come up will see
540 * the startup code even if the caches are disabled
541 */
542 wbinvd();
543
544 /* Start the APs providing number of APs and the cpus_entered field */
Bin Meng6e6f4ce2015-06-17 11:15:36 +0800545 num_aps = num_cpus - 1;
Simon Glass45b5a372015-04-29 22:25:59 -0600546 ret = start_aps(num_aps, ap_count);
547 if (ret) {
548 mdelay(1000);
549 debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
550 num_aps);
551 return ret;
552 }
553
554 /* Walk the flight plan for the BSP */
555 ret = bsp_do_flight_plan(cpu, p);
556 if (ret) {
557 debug("CPU init failed: err=%d\n", ret);
558 return ret;
559 }
560
561 return 0;
562}
563
564int mp_init_cpu(struct udevice *cpu, void *unused)
565{
Simon Glass6bcb6752016-03-11 22:07:09 -0700566 struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
567
Bin Mengecfeada2015-08-09 23:58:39 -0700568 /*
569 * Multiple APs are brought up simultaneously and they may get the same
570 * seq num in the uclass_resolve_seq() during device_probe(). To avoid
571 * this, set req_seq to the reg number in the device tree in advance.
572 */
573 cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1);
Simon Glass6bcb6752016-03-11 22:07:09 -0700574 plat->ucode_version = microcode_read_rev();
575 plat->device_id = gd->arch.x86_device;
Bin Mengecfeada2015-08-09 23:58:39 -0700576
Simon Glass45b5a372015-04-29 22:25:59 -0600577 return device_probe(cpu);
578}