| Jagan Teki | 1494cc8 | 2018-05-07 11:21:34 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2018 BTicino |
| 4 | * Copyright (C) 2018 Amarula Solutions B.V. |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
| 9 | #include <dt-bindings/gpio/gpio.h> |
| 10 | #include "imx6dl.dtsi" |
| 11 | |
| 12 | / { |
| 13 | model = "BTicino i.MX6DL Mamoj board"; |
| 14 | compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; |
| 15 | }; |
| 16 | |
| 17 | &fec { |
| 18 | pinctrl-names = "default"; |
| 19 | pinctrl-0 = <&pinctrl_enet>; |
| 20 | phy-mode = "mii"; |
| 21 | status = "okay"; |
| 22 | }; |
| 23 | |
| Jagan Teki | dda9892 | 2018-05-07 11:21:35 +0530 | [diff] [blame^] | 24 | &i2c3 { |
| 25 | clock-frequency = <400000>; |
| 26 | pinctrl-names = "default"; |
| 27 | pinctrl-0 = <&pinctrl_i2c3>; |
| 28 | status = "okay"; |
| 29 | }; |
| 30 | |
| 31 | &i2c4 { |
| 32 | clock-frequency = <100000>; |
| 33 | pinctrl-names = "default"; |
| 34 | pinctrl-0 = <&pinctrl_i2c4>; |
| 35 | status = "okay"; |
| 36 | }; |
| 37 | |
| Jagan Teki | 1494cc8 | 2018-05-07 11:21:34 +0530 | [diff] [blame] | 38 | &uart3 { |
| 39 | pinctrl-names = "default"; |
| 40 | pinctrl-0 = <&pinctrl_uart3>; |
| 41 | status = "okay"; |
| 42 | }; |
| 43 | |
| 44 | &usdhc3 { |
| 45 | pinctrl-names = "default"; |
| 46 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 47 | bus-width = <8>; |
| 48 | non-removable; |
| 49 | keep-power-in-suspend; |
| 50 | status = "okay"; |
| 51 | }; |
| 52 | |
| 53 | &iomuxc { |
| 54 | pinctrl_enet: enetgrp { |
| 55 | fsl,pins = < |
| 56 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| 57 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| 58 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1 |
| 59 | MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 |
| 60 | MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 |
| 61 | MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0 |
| 62 | MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0 |
| 63 | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 |
| 64 | MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0 |
| 65 | MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1 |
| 66 | MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 |
| 67 | MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 |
| 68 | MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0 |
| 69 | MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0 |
| 70 | MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 |
| 71 | MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 |
| 72 | MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0 |
| 73 | MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0 |
| 74 | >; |
| 75 | }; |
| 76 | |
| Jagan Teki | dda9892 | 2018-05-07 11:21:35 +0530 | [diff] [blame^] | 77 | pinctrl_i2c3: i2c3grp { |
| 78 | fsl,pins = < |
| 79 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 |
| 80 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 |
| 81 | >; |
| 82 | }; |
| 83 | |
| 84 | pinctrl_i2c4: i2c4grp { |
| 85 | fsl,pins = < |
| 86 | MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 |
| 87 | MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 |
| 88 | >; |
| 89 | }; |
| 90 | |
| Jagan Teki | 1494cc8 | 2018-05-07 11:21:34 +0530 | [diff] [blame] | 91 | pinctrl_uart3: uart3grp { |
| 92 | fsl,pins = < |
| 93 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 |
| 94 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 |
| 95 | >; |
| 96 | }; |
| 97 | |
| 98 | pinctrl_usdhc3: usdhc3grp { |
| 99 | fsl,pins = < |
| 100 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 101 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 102 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 103 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 104 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 105 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| 106 | MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
| 107 | MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
| 108 | MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
| 109 | MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
| 110 | >; |
| 111 | }; |
| 112 | }; |