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Stefan Roese8e1a3fe2008-03-11 16:51:17 +01001/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese8e1a3fe2008-03-11 16:51:17 +01006 */
7
8#include <common.h>
Stefan Roeseb36df562010-09-09 19:18:00 +02009#include <asm/ppc440.h>
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010010#include <libfdt.h>
11#include <fdt_support.h>
Stefan Roese212ed902008-06-10 15:34:11 +020012#include <i2c.h>
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010013#include <asm/processor.h>
14#include <asm/io.h>
15#include <asm/mmu.h>
16#include <asm/4xx_pcie.h>
Stefan Roese09887762010-09-16 14:30:37 +020017#include <asm/ppc4xx-gpio.h>
Stefan Roese06dfaee2009-10-02 14:35:16 +020018#include <asm/errno.h>
Mateusz Zalega16297cf2013-10-04 19:22:26 +020019#include <usb.h>
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010020
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020021extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
Stefan Roese8e1a3fe2008-03-11 16:51:17 +010022
23DECLARE_GLOBAL_DATA_PTR;
24
Stefan Roese98303292010-09-28 08:06:06 +020025struct board_bcsr {
26 u8 board_id;
27 u8 cpld_rev;
28 u8 led_user;
29 u8 board_status;
30 u8 reset_ctrl;
31 u8 flash_ctrl;
32 u8 eth_ctrl;
33 u8 usb_ctrl;
34 u8 irq_ctrl;
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +053035};
Stefan Roesecc8e8392008-03-28 14:09:04 +010036
37#define BOARD_CANYONLANDS_PCIE 1
38#define BOARD_CANYONLANDS_SATA 2
39#define BOARD_GLACIER 3
Adam Grahamf09f09d2008-10-08 10:12:53 -070040#define BOARD_ARCHES 4
41
Stefan Roesef3ed3c92009-07-27 10:53:43 +020042/*
Stefan Roesea47a12b2010-04-15 16:07:28 +020043 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
Stefan Roesef3ed3c92009-07-27 10:53:43 +020044 * board specific values.
45 */
46#if defined(CONFIG_ARCHES)
47u32 ddr_wrdtr(u32 default_val) {
48 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
49}
50#else
51u32 ddr_wrdtr(u32 default_val) {
52 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
53}
54
55u32 ddr_clktr(u32 default_val) {
56 return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
57}
58#endif
59
Adam Grahamf09f09d2008-10-08 10:12:53 -070060#if defined(CONFIG_ARCHES)
61/*
62 * FPGA read/write helper macros
63 */
64static inline int board_fpga_read(int offset)
65{
66 int data;
67
68 data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
69
70 return data;
71}
72
73static inline void board_fpga_write(int offset, int data)
74{
75 out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
76}
77
78/*
79 * CPLD read/write helper macros
80 */
81static inline int board_cpld_read(int offset)
82{
83 int data;
84
85 out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
86 data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
87
88 return data;
89}
90
91static inline void board_cpld_write(int offset, int data)
92{
93 out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
94 out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
95}
Stefan Roesec3fa4f02009-07-29 08:46:10 +020096#else
97static int pvr_460ex(void)
98{
99 u32 pvr = get_pvr();
100
101 if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
102 (pvr == PVR_460EX_RB))
103 return 1;
104
105 return 0;
106}
Adam Grahamf09f09d2008-10-08 10:12:53 -0700107#endif /* defined(CONFIG_ARCHES) */
Stefan Roesecc8e8392008-03-28 14:09:04 +0100108
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100109int board_early_init_f(void)
110{
Adam Grahamf09f09d2008-10-08 10:12:53 -0700111#if !defined(CONFIG_ARCHES)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100112 u32 sdr0_cust0;
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530113 struct board_bcsr *bcsr_data =
114 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
115
Adam Grahamf09f09d2008-10-08 10:12:53 -0700116#endif
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100117
Stefan Roese1c2926a2008-04-02 08:39:33 +0200118 /*
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100119 * Setup the interrupt controller polarities, triggers, etc.
Stefan Roese1c2926a2008-04-02 08:39:33 +0200120 */
Stefan Roese952e7762009-09-24 09:55:50 +0200121 mtdcr(UIC0SR, 0xffffffff); /* clear all */
122 mtdcr(UIC0ER, 0x00000000); /* disable all */
123 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
124 mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
125 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
126 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
127 mtdcr(UIC0SR, 0xffffffff); /* clear all */
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100128
Stefan Roese952e7762009-09-24 09:55:50 +0200129 mtdcr(UIC1SR, 0xffffffff); /* clear all */
130 mtdcr(UIC1ER, 0x00000000); /* disable all */
131 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
132 mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
133 mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
134 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
135 mtdcr(UIC1SR, 0xffffffff); /* clear all */
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100136
Stefan Roese952e7762009-09-24 09:55:50 +0200137 mtdcr(UIC2SR, 0xffffffff); /* clear all */
138 mtdcr(UIC2ER, 0x00000000); /* disable all */
139 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
140 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
141 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
142 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
143 mtdcr(UIC2SR, 0xffffffff); /* clear all */
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100144
Stefan Roese952e7762009-09-24 09:55:50 +0200145 mtdcr(UIC3SR, 0xffffffff); /* clear all */
146 mtdcr(UIC3ER, 0x00000000); /* disable all */
147 mtdcr(UIC3CR, 0x00000000); /* all non-critical */
148 mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
149 mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
150 mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
151 mtdcr(UIC3SR, 0xffffffff); /* clear all */
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100152
Adam Grahamf09f09d2008-10-08 10:12:53 -0700153#if !defined(CONFIG_ARCHES)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100154 /* SDR Setting - enable NDFC */
155 mfsdr(SDR0_CUST0, sdr0_cust0);
156 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
157 SDR0_CUST0_NDFC_ENABLE |
158 SDR0_CUST0_NDFC_BW_8_BIT |
159 SDR0_CUST0_NDFC_ARE_MASK |
160 SDR0_CUST0_NDFC_BAC_ENCODE(3) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100162 mtsdr(SDR0_CUST0, sdr0_cust0);
Adam Grahamf09f09d2008-10-08 10:12:53 -0700163#endif
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100164
165 /*
166 * Configure PFC (Pin Function Control) registers
167 * UART0: 4 pins
168 */
169 mtsdr(SDR0_PFC1, 0x00040000);
170
171 /* Enable PCI host functionality in SDR0_PCI0 */
172 mtsdr(SDR0_PCI0, 0xe0000000);
173
Adam Grahamf09f09d2008-10-08 10:12:53 -0700174#if !defined(CONFIG_ARCHES)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100175 /* Enable ethernet and take out of reset */
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530176 out_8(&bcsr_data->eth_ctrl, 0) ;
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100177
178 /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530179 out_8(&bcsr_data->flash_ctrl, 0) ;
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100180 mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
181
Stefan Roese41712b42008-03-05 12:31:53 +0100182 /* Setup PLB4-AHB bridge based on the system address map */
183 mtdcr(AHB_TOP, 0x8000004B);
184 mtdcr(AHB_BOT, 0x8000004B);
185
Adam Grahamf09f09d2008-10-08 10:12:53 -0700186#endif
Stefan Roese41712b42008-03-05 12:31:53 +0100187
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100188 return 0;
189}
190
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530191#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
Troy Kiskybba67912013-10-10 15:27:55 -0700192int board_usb_init(int index, enum usb_init_type init)
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530193{
194 struct board_bcsr *bcsr_data =
195 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
196 u8 val;
197
198 /* Enable USB host & USB-OTG */
199 val = in_8(&bcsr_data->usb_ctrl);
200 val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
201 out_8(&bcsr_data->usb_ctrl, val);
202
Rupjyoti Sarmah709d9482010-10-01 14:31:28 +0530203 /*
204 * Configure USB-STP pins as alternate and not GPIO
205 * It seems to be neccessary to configure the STP pins as GPIO
206 * input at powerup (perhaps while USB reset is asserted). So
207 * we configure those pins to their "real" function now.
208 */
209 gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
210 gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
211
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530212 return 0;
213}
214
215int usb_board_stop(void)
216{
217 struct board_bcsr *bcsr_data =
218 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
219 u8 val;
220
221 /* Disable USB host & USB-OTG */
222 val = in_8(&bcsr_data->usb_ctrl);
223 val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
224 out_8(&bcsr_data->usb_ctrl, val);
225
Rupjyoti Sarmah709d9482010-10-01 14:31:28 +0530226 /* Reconfigure USB-STP pins as input */
227 gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
228 gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
229
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530230 return 0;
231}
232
Troy Kiskybba67912013-10-10 15:27:55 -0700233int board_usb_cleanup(int index, enum usb_init_type init)
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530234{
235 return usb_board_stop();
236}
237#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
238
Adam Grahamf09f09d2008-10-08 10:12:53 -0700239#if !defined(CONFIG_ARCHES)
Stefan Roese1c2926a2008-04-02 08:39:33 +0200240static void canyonlands_sata_init(int board_type)
241{
242 u32 reg;
243
244 if (board_type == BOARD_CANYONLANDS_SATA) {
245 /* Put SATA in reset */
246 SDR_WRITE(SDR0_SRST1, 0x00020001);
247
248 /* Set the phy for SATA, not PCI-E port 0 */
249 reg = SDR_READ(PESDR0_PHY_CTL_RST);
250 SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
251 reg = SDR_READ(PESDR0_L0CLK);
252 SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
253 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
254 SDR_WRITE(PESDR0_L0DRV, 0x00000104);
255
256 /* Bring SATA out of reset */
257 SDR_WRITE(SDR0_SRST1, 0x00000000);
258 }
259}
Adam Grahamf09f09d2008-10-08 10:12:53 -0700260#endif /* !defined(CONFIG_ARCHES) */
Stefan Roese1c2926a2008-04-02 08:39:33 +0200261
Adam Grahamf09f09d2008-10-08 10:12:53 -0700262int get_cpu_num(void)
263{
264 int cpu = NA_OR_UNKNOWN_CPU;
265
266#if defined(CONFIG_ARCHES)
267 int cpu_num;
268
269 cpu_num = board_fpga_read(0x3);
270
271 /* sanity check; assume cpu numbering starts and increments from 0 */
272 if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
273 cpu = cpu_num;
274#endif
275
276 return cpu;
277}
278
279#if !defined(CONFIG_ARCHES)
Stefan Roese1c2926a2008-04-02 08:39:33 +0200280int checkboard(void)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100281{
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530282 struct board_bcsr *bcsr_data =
283 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000284 char buf[64];
285 int i = getenv_f("serial#", buf, sizeof(buf));
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100286
Stefan Roesec3fa4f02009-07-29 08:46:10 +0200287 if (pvr_460ex()) {
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100288 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530289 if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
Stefan Roesecc8e8392008-03-28 14:09:04 +0100290 gd->board_type = BOARD_CANYONLANDS_PCIE;
291 else
292 gd->board_type = BOARD_CANYONLANDS_SATA;
Stefan Roesec3fa4f02009-07-29 08:46:10 +0200293 } else {
294 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
295 gd->board_type = BOARD_GLACIER;
Stefan Roesecc8e8392008-03-28 14:09:04 +0100296 }
297
298 switch (gd->board_type) {
299 case BOARD_CANYONLANDS_PCIE:
300 case BOARD_GLACIER:
301 puts(", 2*PCIe");
302 break;
303
304 case BOARD_CANYONLANDS_SATA:
305 puts(", 1*PCIe/1*SATA");
306 break;
307 }
308
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530309 printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100310
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000311 if (i > 0) {
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100312 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000313 puts(buf);
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100314 }
315 putc('\n');
316
Stefan Roese1c2926a2008-04-02 08:39:33 +0200317 canyonlands_sata_init(gd->board_type);
318
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100319 return (0);
320}
321
Adam Grahamf09f09d2008-10-08 10:12:53 -0700322#else /* defined(CONFIG_ARCHES) */
323
324int checkboard(void)
325{
326 char *s = getenv("serial#");
327
328 printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
329 printf(" Revision %02x.%02x ",
330 board_fpga_read(0x0), board_fpga_read(0x1));
331
332 gd->board_type = BOARD_ARCHES;
333
334 /* Only CPU0 has access to CPLD registers */
335 if (get_cpu_num() == 0) {
336 u8 cfg_sw = board_cpld_read(0x1);
337 printf("(FPGA=%02x, CPLD=%02x)\n",
338 board_fpga_read(0x2), board_cpld_read(0x0));
339 printf(" Configuration Switch %d%d%d%d\n",
340 ((cfg_sw >> 3) & 0x01),
341 ((cfg_sw >> 2) & 0x01),
342 ((cfg_sw >> 1) & 0x01),
343 ((cfg_sw >> 0) & 0x01));
344 } else
345 printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
346
347
348 if (s != NULL)
349 printf(" Serial# %s\n", s);
350
351 return 0;
352}
353#endif /* !defined(CONFIG_ARCHES) */
354
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100355#if defined(CONFIG_PCI)
Stefan Roeseb0b86742009-10-29 15:04:35 +0100356int board_pcie_first(void)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100357{
Stefan Roesecc8e8392008-03-28 14:09:04 +0100358 /*
359 * Canyonlands with SATA enabled has only one PCIe slot
360 * (2nd one).
361 */
362 if (gd->board_type == BOARD_CANYONLANDS_SATA)
Stefan Roeseb0b86742009-10-29 15:04:35 +0100363 return 1;
Stefan Roesecc8e8392008-03-28 14:09:04 +0100364
Stefan Roeseb0b86742009-10-29 15:04:35 +0100365 return 0;
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100366}
367#endif /* CONFIG_PCI */
368
369int board_early_init_r (void)
370{
371 /*
372 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
373 * boot EBC mapping only supports a maximum of 16MBytes
374 * (4.ff00.0000 - 4.ffff.ffff).
375 * To solve this problem, the FLASH has to get remapped to another
376 * EBC address which accepts bigger regions:
377 *
378 * 0xfc00.0000 -> 4.cc00.0000
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100379 */
380
381 /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200382 mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100383
384 /* Remove TLB entry of boot EBC mapping */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385 remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100386
387 /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388 program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100389 TLB_WORD2_I_ENABLE);
390
391 /*
392 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
393 * 0xfc00.0000 is possible
394 */
395
Stefan Roese71665eb2008-03-03 17:27:02 +0100396 /*
397 * Clear potential errors resulting from auto-calibration.
398 * If not done, then we could get an interrupt later on when
399 * exceptions are enabled.
400 */
401 set_mcsr(get_mcsr());
402
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100403 return 0;
404}
405
Adam Grahamf09f09d2008-10-08 10:12:53 -0700406#if !defined(CONFIG_ARCHES)
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100407int misc_init_r(void)
408{
409 u32 sdr0_srst1 = 0;
410 u32 eth_cfg;
Stefan Roese212ed902008-06-10 15:34:11 +0200411 u8 val;
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100412
413 /*
414 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
415 * This is board specific, so let's do it here.
416 */
417 mfsdr(SDR0_ETH_CFG, eth_cfg);
418 /* disable SGMII mode */
419 eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
420 SDR0_ETH_CFG_SGMII1_ENABLE |
421 SDR0_ETH_CFG_SGMII0_ENABLE);
422 /* Set the for 2 RGMII mode */
423 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
424 eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
Stefan Roesec3fa4f02009-07-29 08:46:10 +0200425 if (pvr_460ex())
Stefan Roese4c9e8552008-03-19 16:20:49 +0100426 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
427 else
428 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100429 mtsdr(SDR0_ETH_CFG, eth_cfg);
430
431 /*
432 * The AHB Bridge core is held in reset after power-on or reset
433 * so enable it now
434 */
435 mfsdr(SDR0_SRST1, sdr0_srst1);
436 sdr0_srst1 &= ~SDR0_SRST1_AHB;
437 mtsdr(SDR0_SRST1, sdr0_srst1);
438
Stefan Roese212ed902008-06-10 15:34:11 +0200439 /*
440 * RTC/M41T62:
441 * Disable square wave output: Batterie will be drained
442 * quickly, when this output is not disabled
443 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444 val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
Stefan Roese212ed902008-06-10 15:34:11 +0200445 val &= ~0x40;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446 i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
Stefan Roese212ed902008-06-10 15:34:11 +0200447
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100448 return 0;
449}
450
Adam Grahamf09f09d2008-10-08 10:12:53 -0700451#else /* defined(CONFIG_ARCHES) */
452
453int misc_init_r(void)
454{
455 u32 eth_cfg = 0;
456 u32 eth_pll;
457 u32 reg;
458
459 /*
460 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
461 * This is board specific, so let's do it here.
462 */
463
464 /* enable SGMII mode */
465 eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
466 SDR0_ETH_CFG_SGMII1_ENABLE |
467 SDR0_ETH_CFG_SGMII2_ENABLE);
468
469 /* Set EMAC for MDIO */
470 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
471
472 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
473 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
474
475 mtsdr(SDR0_ETH_CFG, eth_cfg);
476
477 /* reset all SGMII interfaces */
478 mfsdr(SDR0_SRST1, reg);
479 reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
480 mtsdr(SDR0_SRST1, reg);
481 mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
482 mtsdr(SDR0_SRST1, 0x00000000);
483
484 do {
485 mfsdr(SDR0_ETH_PLL, eth_pll);
486 } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
487
488 return 0;
489}
490#endif /* !defined(CONFIG_ARCHES) */
491
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100492#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Felix Radensky26d37f02009-06-22 15:30:42 +0300493extern void __ft_board_setup(void *blob, bd_t *bd);
494
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100495void ft_board_setup(void *blob, bd_t *bd)
496{
Felix Radensky26d37f02009-06-22 15:30:42 +0300497 __ft_board_setup(blob, bd);
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100498
Stefan Roese16bedc62008-05-19 07:14:38 +0200499 if (gd->board_type == BOARD_CANYONLANDS_SATA) {
500 /*
501 * When SATA is selected we need to disable the first PCIe
502 * node in the device tree, so that Linux doesn't initialize
503 * it.
504 */
Stefan Roese8fd41662008-09-22 16:10:43 +0200505 fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
506 "disabled", sizeof("disabled"), 1);
Stefan Roese16bedc62008-05-19 07:14:38 +0200507 }
508
509 if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
510 /*
511 * When PCIe is selected we need to disable the SATA
512 * node in the device tree, so that Linux doesn't initialize
513 * it.
514 */
Stefan Roese8fd41662008-09-22 16:10:43 +0200515 fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
516 "disabled", sizeof("disabled"), 1);
Stefan Roese16bedc62008-05-19 07:14:38 +0200517 }
Stefan Roese8e1a3fe2008-03-11 16:51:17 +0100518}
519#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */