blob: d4d277ba6d3c1ba866a1a1a8dfdd0f551167625f [file] [log] [blame]
Chunhe Lan57072332013-06-14 16:21:48 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
5 * Chunhe Lan <Chunhe.Lan@freescale.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Chunhe Lan57072332013-06-14 16:21:48 +08008 */
9
10#include <common.h>
11#include <command.h>
12#include <pci.h>
13#include <asm/io.h>
14#include <asm/cache.h>
15#include <asm/processor.h>
16#include <asm/mmu.h>
17#include <asm/immap_85xx.h>
18#include <asm/fsl_pci.h>
York Sun5614e712013-09-30 09:22:09 -070019#include <fsl_ddr_sdram.h>
Chunhe Lan57072332013-06-14 16:21:48 +080020#include <asm/fsl_portals.h>
21#include <libfdt.h>
22#include <fdt_support.h>
23#include <netdev.h>
24#include <malloc.h>
25#include <fm_eth.h>
26#include <fsl_mdio.h>
27#include <miiphy.h>
28#include <phy.h>
29#include <asm/fsl_dtsec.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
33int board_early_init_f(void)
34{
35 fsl_lbc_t *lbc = LBC_BASE_ADDR;
36
37 /* Set ABSWP to implement conversion of addresses in the LBC */
38 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
39
40 return 0;
41}
42
43int checkboard(void)
44{
45 printf("Board: P1023 RDB\n");
46
47 return 0;
48}
49
50#ifdef CONFIG_PCI
51void pci_init_board(void)
52{
53 fsl_pcie_init_board(0);
54}
55#endif
56
57int board_early_init_r(void)
58{
59 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun9d045682014-06-24 21:16:20 -070060 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Chunhe Lan57072332013-06-14 16:21:48 +080061
62 /*
63 * Remap Boot flash + PROMJET region to caching-inhibited
64 * so that flash can be erased properly.
65 */
66
67 /* Flush d-cache and invalidate i-cache of any FLASH data */
68 flush_dcache();
69 invalidate_icache();
70
York Sun9d045682014-06-24 21:16:20 -070071 if (flash_esel == -1) {
72 /* very unlikely unless something is messed up */
73 puts("Error: Could not find TLB for FLASH BASE\n");
74 flash_esel = 2; /* give our best effort to continue */
75 } else {
76 /* invalidate existing TLB entry for flash + promjet */
77 disable_tlb(flash_esel);
78 }
Chunhe Lan57072332013-06-14 16:21:48 +080079
80 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
81 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
82 0, flash_esel, BOOKE_PAGESZ_256M, 1);
83
84 setup_portals();
85
86 return 0;
87}
88
89unsigned long get_board_sys_clk(ulong dummy)
90{
91 return gd->bus_clk;
92}
93
94unsigned long get_board_ddr_clk(ulong dummy)
95{
96 return gd->mem_clk;
97}
98
99int board_eth_init(bd_t *bis)
100{
101 ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
102 struct fsl_pq_mdio_info dtsec_mdio_info;
103
104 /*
105 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
106 * is not correct.
107 */
108 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
109
110 dtsec_mdio_info.regs =
111 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
112 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
113
114 /* Register the 1G MDIO bus */
115 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
116
117 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
118 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
119
120 fm_info_set_mdio(FM1_DTSEC1,
121 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
122 fm_info_set_mdio(FM1_DTSEC2,
123 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
124
125#ifdef CONFIG_FMAN_ENET
126 cpu_eth_init(bis);
127#endif
128
129 return pci_eth_init(bis);
130}
131
132#if defined(CONFIG_OF_BOARD_SETUP)
133void ft_board_setup(void *blob, bd_t *bd)
134{
135 phys_addr_t base;
136 phys_size_t size;
137
138 ft_cpu_setup(blob, bd);
139
140 base = getenv_bootm_low();
141 size = getenv_bootm_size();
142
143 fdt_fixup_memory(blob, (u64)base, (u64)size);
144
145#ifdef CONFIG_HAS_FSL_DR_USB
146 fdt_fixup_dr_usb(blob, bd);
147#endif
148
149 fdt_fixup_fman_ethernet(blob);
150}
151#endif