blob: bd83a249ee34a3ca3291dc1cac5aa6290ec6cca5 [file] [log] [blame]
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001/*
2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <net.h>
27#include <miiphy.h>
28#include "fec_mxc.h"
29
30#include <asm/arch/clock.h>
31#include <asm/arch/imx-regs.h>
32#include <asm/io.h>
33#include <asm/errno.h>
34
35DECLARE_GLOBAL_DATA_PTR;
36
37#ifndef CONFIG_MII
38#error "CONFIG_MII has to be defined!"
39#endif
40
41#undef DEBUG
42
43struct nbuf {
44 uint8_t data[1500]; /**< actual data */
45 int length; /**< actual length */
46 int used; /**< buffer in use or not */
47 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
48};
49
50struct fec_priv gfec = {
51 .eth = (struct ethernet_regs *)IMX_FEC_BASE,
52 .xcv_type = MII100,
53 .rbd_base = NULL,
54 .rbd_index = 0,
55 .tbd_base = NULL,
56 .tbd_index = 0,
57 .bd = NULL,
58};
59
60/*
61 * MII-interface related functions
62 */
63static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
64 uint16_t *retVal)
65{
66 struct eth_device *edev = eth_get_dev_by_name(dev);
67 struct fec_priv *fec = (struct fec_priv *)edev->priv;
68
69 uint32_t reg; /* convenient holder for the PHY register */
70 uint32_t phy; /* convenient holder for the PHY */
71 uint32_t start;
72
73 /*
74 * reading from any PHY's register is done by properly
75 * programming the FEC's MII data register.
76 */
77 writel(FEC_IEVENT_MII, &fec->eth->ievent);
78 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
79 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
80
81 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
82 phy | reg, &fec->eth->mii_data);
83
84 /*
85 * wait for the related interrupt
86 */
87 start = get_timer_masked();
88 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
89 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
90 printf("Read MDIO failed...\n");
91 return -1;
92 }
93 }
94
95 /*
96 * clear mii interrupt bit
97 */
98 writel(FEC_IEVENT_MII, &fec->eth->ievent);
99
100 /*
101 * it's now safe to read the PHY's register
102 */
103 *retVal = readl(&fec->eth->mii_data);
104 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
105 regAddr, *retVal);
106 return 0;
107}
108
109static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
110 uint16_t data)
111{
112 struct eth_device *edev = eth_get_dev_by_name(dev);
113 struct fec_priv *fec = (struct fec_priv *)edev->priv;
114
115 uint32_t reg; /* convenient holder for the PHY register */
116 uint32_t phy; /* convenient holder for the PHY */
117 uint32_t start;
118
119 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
120 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
121
122 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
123 FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
124
125 /*
126 * wait for the MII interrupt
127 */
128 start = get_timer_masked();
129 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
130 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
131 printf("Write MDIO failed...\n");
132 return -1;
133 }
134 }
135
136 /*
137 * clear MII interrupt bit
138 */
139 writel(FEC_IEVENT_MII, &fec->eth->ievent);
140 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
141 regAddr, data);
142
143 return 0;
144}
145
146static int miiphy_restart_aneg(struct eth_device *dev)
147{
148 /*
149 * Wake up from sleep if necessary
150 * Reset PHY, then delay 300ns
151 */
152 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
153 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
154 PHY_BMCR_RESET);
155 udelay(1000);
156
157 /*
158 * Set the auto-negotiation advertisement register bits
159 */
160 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 0x1e0);
161 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
162 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
163
164 return 0;
165}
166
167static int miiphy_wait_aneg(struct eth_device *dev)
168{
169 uint32_t start;
170 uint16_t status;
171
172 /*
173 * Wait for AN completion
174 */
175 start = get_timer_masked();
176 do {
177 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
178 printf("%s: Autonegotiation timeout\n", dev->name);
179 return -1;
180 }
181
182 if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
183 PHY_BMSR, &status)) {
184 printf("%s: Autonegotiation failed. status: 0x%04x\n",
185 dev->name, status);
186 return -1;
187 }
188 } while (!(status & PHY_BMSR_LS));
189
190 return 0;
191}
192static int fec_rx_task_enable(struct fec_priv *fec)
193{
194 writel(1 << 24, &fec->eth->r_des_active);
195 return 0;
196}
197
198static int fec_rx_task_disable(struct fec_priv *fec)
199{
200 return 0;
201}
202
203static int fec_tx_task_enable(struct fec_priv *fec)
204{
205 writel(1 << 24, &fec->eth->x_des_active);
206 return 0;
207}
208
209static int fec_tx_task_disable(struct fec_priv *fec)
210{
211 return 0;
212}
213
214/**
215 * Initialize receive task's buffer descriptors
216 * @param[in] fec all we know about the device yet
217 * @param[in] count receive buffer count to be allocated
218 * @param[in] size size of each receive buffer
219 * @return 0 on success
220 *
221 * For this task we need additional memory for the data buffers. And each
222 * data buffer requires some alignment. Thy must be aligned to a specific
223 * boundary each (DB_DATA_ALIGNMENT).
224 */
225static int fec_rbd_init(struct fec_priv *fec, int count, int size)
226{
227 int ix;
228 uint32_t p = 0;
229
230 /* reserve data memory and consider alignment */
231 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
232 p = (uint32_t)fec->rdb_ptr;
233 if (!p) {
234 puts("fec_imx27: not enough malloc memory!\n");
235 return -ENOMEM;
236 }
237 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
238 p += DB_DATA_ALIGNMENT-1;
239 p &= ~(DB_DATA_ALIGNMENT-1);
240
241 for (ix = 0; ix < count; ix++) {
242 writel(p, &fec->rbd_base[ix].data_pointer);
243 p += size;
244 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
245 writew(0, &fec->rbd_base[ix].data_length);
246 }
247 /*
248 * mark the last RBD to close the ring
249 */
250 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
251 fec->rbd_index = 0;
252
253 return 0;
254}
255
256/**
257 * Initialize transmit task's buffer descriptors
258 * @param[in] fec all we know about the device yet
259 *
260 * Transmit buffers are created externally. We only have to init the BDs here.\n
261 * Note: There is a race condition in the hardware. When only one BD is in
262 * use it must be marked with the WRAP bit to use it for every transmitt.
263 * This bit in combination with the READY bit results into double transmit
264 * of each data buffer. It seems the state machine checks READY earlier then
265 * resetting it after the first transfer.
266 * Using two BDs solves this issue.
267 */
268static void fec_tbd_init(struct fec_priv *fec)
269{
270 writew(0x0000, &fec->tbd_base[0].status);
271 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
272 fec->tbd_index = 0;
273}
274
275/**
276 * Mark the given read buffer descriptor as free
277 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
278 * @param[in] pRbd buffer descriptor to mark free again
279 */
280static void fec_rbd_clean(int last, struct fec_bd *pRbd)
281{
282 /*
283 * Reset buffer descriptor as empty
284 */
285 if (last)
286 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
287 else
288 writew(FEC_RBD_EMPTY, &pRbd->status);
289 /*
290 * no data in it
291 */
292 writew(0, &pRbd->data_length);
293}
294
295static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
296{
297 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
298 int i;
299
300 for (i = 0; i < 6; i++)
301 mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);
302
303 return is_valid_ether_addr(mac);
304}
305
306static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
307{
308 struct fec_priv *fec = (struct fec_priv *)dev->priv;
309
310 writel(0, &fec->eth->iaddr1);
311 writel(0, &fec->eth->iaddr2);
312 writel(0, &fec->eth->gaddr1);
313 writel(0, &fec->eth->gaddr2);
314
315 /*
316 * Set physical address
317 */
318 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
319 &fec->eth->paddr1);
320 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
321
322 return 0;
323}
324
325/**
326 * Start the FEC engine
327 * @param[in] dev Our device to handle
328 */
329static int fec_open(struct eth_device *edev)
330{
331 struct fec_priv *fec = (struct fec_priv *)edev->priv;
332
333 debug("fec_open: fec_open(dev)\n");
334 /* full-duplex, heartbeat disabled */
335 writel(1 << 2, &fec->eth->x_cntrl);
336 fec->rbd_index = 0;
337
338 /*
339 * Enable FEC-Lite controller
340 */
341 writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
342
343 miiphy_wait_aneg(edev);
344 miiphy_speed(edev->name, 0);
345 miiphy_duplex(edev->name, 0);
346
347 /*
348 * Enable SmartDMA receive task
349 */
350 fec_rx_task_enable(fec);
351
352 udelay(100000);
353 return 0;
354}
355
356static int fec_init(struct eth_device *dev, bd_t* bd)
357{
358 uint32_t base;
359 struct fec_priv *fec = (struct fec_priv *)dev->priv;
360
361 /*
362 * reserve memory for both buffer descriptor chains at once
363 * Datasheet forces the startaddress of each chain is 16 byte
364 * aligned
365 */
366 fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
367 sizeof(struct fec_bd) + DB_ALIGNMENT);
368 base = (uint32_t)fec->base_ptr;
369 if (!base) {
370 puts("fec_imx27: not enough malloc memory!\n");
371 return -ENOMEM;
372 }
373 memset((void *)base, 0, (2 + FEC_RBD_NUM) *
374 sizeof(struct fec_bd) + DB_ALIGNMENT);
375 base += (DB_ALIGNMENT-1);
376 base &= ~(DB_ALIGNMENT-1);
377
378 fec->rbd_base = (struct fec_bd *)base;
379
380 base += FEC_RBD_NUM * sizeof(struct fec_bd);
381
382 fec->tbd_base = (struct fec_bd *)base;
383
384 /*
385 * Set interrupt mask register
386 */
387 writel(0x00000000, &fec->eth->imask);
388
389 /*
390 * Clear FEC-Lite interrupt event register(IEVENT)
391 */
392 writel(0xffffffff, &fec->eth->ievent);
393
394
395 /*
396 * Set FEC-Lite receive control register(R_CNTRL):
397 */
398 if (fec->xcv_type == SEVENWIRE) {
399 /*
400 * Frame length=1518; 7-wire mode
401 */
402 writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */
403 } else {
404 /*
405 * Frame length=1518; MII mode;
406 */
407 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
408 /*
409 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
410 * and do not drop the Preamble.
411 */
412 writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
413 &fec->eth->mii_speed);
414 debug("fec_init: mii_speed %#lx\n",
415 (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
416 }
417 /*
418 * Set Opcode/Pause Duration Register
419 */
420 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
421 writel(0x2, &fec->eth->x_wmrk);
422 /*
423 * Set multicast address filter
424 */
425 writel(0x00000000, &fec->eth->gaddr1);
426 writel(0x00000000, &fec->eth->gaddr2);
427
428
429 /* clear MIB RAM */
430 long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
431 while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
432 *mib_ptr++ = 0;
433
434 /* FIFO receive start register */
435 writel(0x520, &fec->eth->r_fstart);
436
437 /* size and address of each buffer */
438 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
439 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
440 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
441
442 /*
443 * Initialize RxBD/TxBD rings
444 */
445 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
446 free(fec->base_ptr);
447 return -ENOMEM;
448 }
449 fec_tbd_init(fec);
450
451
452 if (fec->xcv_type != SEVENWIRE)
453 miiphy_restart_aneg(dev);
454
455 fec_open(dev);
456 return 0;
457}
458
459/**
460 * Halt the FEC engine
461 * @param[in] dev Our device to handle
462 */
463static void fec_halt(struct eth_device *dev)
464{
465 struct fec_priv *fec = &gfec;
466 int counter = 0xffff;
467
468 /*
469 * issue graceful stop command to the FEC transmitter if necessary
470 */
471 writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
472 &fec->eth->x_cntrl);
473
474 debug("eth_halt: wait for stop regs\n");
475 /*
476 * wait for graceful stop to register
477 */
478 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
479 ; /* FIXME ensure time */
480
481 /*
482 * Disable SmartDMA tasks
483 */
484 fec_tx_task_disable(fec);
485 fec_rx_task_disable(fec);
486
487 /*
488 * Disable the Ethernet Controller
489 * Note: this will also reset the BD index counter!
490 */
491 writel(0, &fec->eth->ecntrl);
492 fec->rbd_index = 0;
493 fec->tbd_index = 0;
494 free(fec->rdb_ptr);
495 free(fec->base_ptr);
496 debug("eth_halt: done\n");
497}
498
499/**
500 * Transmit one frame
501 * @param[in] dev Our ethernet device to handle
502 * @param[in] packet Pointer to the data to be transmitted
503 * @param[in] length Data count in bytes
504 * @return 0 on success
505 */
506static int fec_send(struct eth_device *dev, volatile void* packet, int length)
507{
508 unsigned int status;
509
510 /*
511 * This routine transmits one frame. This routine only accepts
512 * 6-byte Ethernet addresses.
513 */
514 struct fec_priv *fec = (struct fec_priv *)dev->priv;
515
516 /*
517 * Check for valid length of data.
518 */
519 if ((length > 1500) || (length <= 0)) {
520 printf("Payload (%d) to large!\n", length);
521 return -1;
522 }
523
524 /*
525 * Setup the transmit buffer
526 * Note: We are always using the first buffer for transmission,
527 * the second will be empty and only used to stop the DMA engine
528 */
529 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
530 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
531 /*
532 * update BD's status now
533 * This block:
534 * - is always the last in a chain (means no chain)
535 * - should transmitt the CRC
536 * - might be the last BD in the list, so the address counter should
537 * wrap (-> keep the WRAP flag)
538 */
539 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
540 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
541 writew(status, &fec->tbd_base[fec->tbd_index].status);
542
543 /*
544 * Enable SmartDMA transmit task
545 */
546 fec_tx_task_enable(fec);
547
548 /*
549 * wait until frame is sent .
550 */
551 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
552 /* FIXME: Timeout */
553 }
554 debug("fec_send: status 0x%x index %d\n",
555 readw(&fec->tbd_base[fec->tbd_index].status),
556 fec->tbd_index);
557 /* for next transmission use the other buffer */
558 if (fec->tbd_index)
559 fec->tbd_index = 0;
560 else
561 fec->tbd_index = 1;
562
563 return 0;
564}
565
566/**
567 * Pull one frame from the card
568 * @param[in] dev Our ethernet device to handle
569 * @return Length of packet read
570 */
571static int fec_recv(struct eth_device *dev)
572{
573 struct fec_priv *fec = (struct fec_priv *)dev->priv;
574 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
575 unsigned long ievent;
576 int frame_length, len = 0;
577 struct nbuf *frame;
578 uint16_t bd_status;
579 uchar buff[FEC_MAX_PKT_SIZE];
580
581 /*
582 * Check if any critical events have happened
583 */
584 ievent = readl(&fec->eth->ievent);
585 writel(ievent, &fec->eth->ievent);
586 debug("fec_recv: ievent 0x%x\n", ievent);
587 if (ievent & FEC_IEVENT_BABR) {
588 fec_halt(dev);
589 fec_init(dev, fec->bd);
590 printf("some error: 0x%08lx\n", ievent);
591 return 0;
592 }
593 if (ievent & FEC_IEVENT_HBERR) {
594 /* Heartbeat error */
595 writel(0x00000001 | readl(&fec->eth->x_cntrl),
596 &fec->eth->x_cntrl);
597 }
598 if (ievent & FEC_IEVENT_GRA) {
599 /* Graceful stop complete */
600 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
601 fec_halt(dev);
602 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
603 &fec->eth->x_cntrl);
604 fec_init(dev, fec->bd);
605 }
606 }
607
608 /*
609 * ensure reading the right buffer status
610 */
611 bd_status = readw(&rbd->status);
612 debug("fec_recv: status 0x%x\n", bd_status);
613
614 if (!(bd_status & FEC_RBD_EMPTY)) {
615 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
616 ((readw(&rbd->data_length) - 4) > 14)) {
617 /*
618 * Get buffer address and size
619 */
620 frame = (struct nbuf *)readl(&rbd->data_pointer);
621 frame_length = readw(&rbd->data_length) - 4;
622 /*
623 * Fill the buffer and pass it to upper layers
624 */
625 memcpy(buff, frame->data, frame_length);
626 NetReceive(buff, frame_length);
627 len = frame_length;
628 } else {
629 if (bd_status & FEC_RBD_ERR)
630 printf("error frame: 0x%08lx 0x%08x\n",
631 (ulong)rbd->data_pointer,
632 bd_status);
633 }
634 /*
635 * free the current buffer, restart the engine
636 * and move forward to the next buffer
637 */
638 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
639 fec_rx_task_enable(fec);
640 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
641 }
642 debug("fec_recv: stop\n");
643
644 return len;
645}
646
647static int fec_probe(bd_t *bd)
648{
649 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
650 struct eth_device *edev;
651 struct fec_priv *fec = &gfec;
652 unsigned char ethaddr_str[20];
653 unsigned char ethaddr[6];
654 char *tmp = getenv("ethaddr");
655 char *end;
656
657 /* enable FEC clock */
658 writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
659 writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
660
661 /* create and fill edev struct */
662 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
663 if (!edev) {
664 puts("fec_imx27: not enough malloc memory!\n");
665 return -ENOMEM;
666 }
667 edev->priv = fec;
668 edev->init = fec_init;
669 edev->send = fec_send;
670 edev->recv = fec_recv;
671 edev->halt = fec_halt;
672
673 fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
674 fec->bd = bd;
675
676 fec->xcv_type = MII100;
677
678 /* Reset chip. */
679 writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
680 while (readl(&fec->eth->ecntrl) & 1)
681 udelay(10);
682
683 /*
684 * Set interrupt mask register
685 */
686 writel(0x00000000, &fec->eth->imask);
687
688 /*
689 * Clear FEC-Lite interrupt event register(IEVENT)
690 */
691 writel(0xffffffff, &fec->eth->ievent);
692
693 /*
694 * Set FEC-Lite receive control register(R_CNTRL):
695 */
696 /*
697 * Frame length=1518; MII mode;
698 */
699 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
700 /*
701 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
702 * and do not drop the Preamble.
703 */
704 writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
705 &fec->eth->mii_speed);
706 debug("fec_init: mii_speed %#lx\n",
707 (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
708
709 sprintf(edev->name, "FEC_MXC");
710
711 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
712
713 eth_register(edev);
714
715 if ((NULL != tmp) && (12 <= strlen(tmp))) {
716 int i;
717 /* convert MAC from string to int */
718 for (i = 0; i < 6; i++) {
719 ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
720 if (tmp)
721 tmp = (*end) ? end + 1 : end;
722 }
723 } else if (fec_get_hwaddr(edev, ethaddr) == 0) {
724 printf("got MAC address from EEPROM: %pM\n", ethaddr);
725 setenv("ethaddr", (char *)ethaddr_str);
726 }
727 memcpy(edev->enetaddr, ethaddr, 6);
728 fec_set_hwaddr(edev, ethaddr);
729
730 return 0;
731}
732
733int fecmxc_initialize(bd_t *bd)
734{
735 int lout = 1;
736
737 debug("eth_init: fec_probe(bd)\n");
738 lout = fec_probe(bd);
739
740 return lout;
741}