blob: 6435bf9ad18f2db0da555004f3ca7808f47edf32 [file] [log] [blame]
Wang Huan550e3dc2014-09-05 13:52:44 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <fsl_ddr_sdram.h>
9#include <fsl_ddr_dimm_params.h>
tang yuantian41ba57d2014-12-17 12:58:05 +080010#include <asm/io.h>
Wang Huan550e3dc2014-09-05 13:52:44 +080011#include "ddr.h"
12
13DECLARE_GLOBAL_DATA_PTR;
14
15void fsl_ddr_board_options(memctl_options_t *popts,
16 dimm_params_t *pdimm,
17 unsigned int ctrl_num)
18{
19 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
20 ulong ddr_freq;
21
22 if (ctrl_num > 3) {
23 printf("Not supported controller number %d\n", ctrl_num);
24 return;
25 }
26 if (!pdimm->n_ranks)
27 return;
28
29 pbsp = udimms[0];
30
31 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
32 * freqency and n_banks specified in board_specific_parameters table.
33 */
34 ddr_freq = get_ddr_freq(0) / 1000000;
35 while (pbsp->datarate_mhz_high) {
36 if (pbsp->n_ranks == pdimm->n_ranks) {
37 if (ddr_freq <= pbsp->datarate_mhz_high) {
38 popts->clk_adjust = pbsp->clk_adjust;
39 popts->wrlvl_start = pbsp->wrlvl_start;
40 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
41 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
42 popts->cpo_override = pbsp->cpo_override;
43 popts->write_data_delay =
44 pbsp->write_data_delay;
45 goto found;
46 }
47 pbsp_highest = pbsp;
48 }
49 pbsp++;
50 }
51
52 if (pbsp_highest) {
53 printf("Error: board specific timing not found for %lu MT/s\n",
54 ddr_freq);
55 printf("Trying to use the highest speed (%u) parameters\n",
56 pbsp_highest->datarate_mhz_high);
57 popts->clk_adjust = pbsp_highest->clk_adjust;
58 popts->wrlvl_start = pbsp_highest->wrlvl_start;
59 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
60 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
61 } else {
62 panic("DIMM is not supported by this board");
63 }
64found:
65 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
66 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
67
68 /* force DDR bus width to 32 bits */
69 popts->data_bus_width = 1;
70 popts->otf_burst_chop_en = 0;
71 popts->burst_length = DDR_BL8;
72
73 /*
74 * Factors to consider for half-strength driver enable:
75 * - number of DIMMs installed
76 */
77 popts->half_strength_driver_enable = 1;
78 /*
79 * Write leveling override
80 */
81 popts->wrlvl_override = 1;
82 popts->wrlvl_sample = 0xf;
Wang Huan550e3dc2014-09-05 13:52:44 +080083
84 /*
85 * Rtt and Rtt_WR override
86 */
87 popts->rtt_override = 0;
88
89 /* Enable ZQ calibration */
90 popts->zq_en = 1;
91
York Sunc7eae7f2014-09-11 13:32:07 -070092#ifdef CONFIG_SYS_FSL_DDR4
93 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
94 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
95 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
96#else
97 popts->cswl_override = DDR_CSWL_CS0;
98
Wang Huan550e3dc2014-09-05 13:52:44 +080099 /* DHC_EN =1, ODT = 75 Ohm */
100 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
101 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
York Sunc7eae7f2014-09-11 13:32:07 -0700102#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800103}
104
105#ifdef CONFIG_SYS_DDR_RAW_TIMING
106dimm_params_t ddr_raw_timing = {
107 .n_ranks = 1,
108 .rank_density = 1073741824u,
109 .capacity = 1073741824u,
110 .primary_sdram_width = 32,
111 .ec_sdram_width = 0,
112 .registered_dimm = 0,
113 .mirrored_dimm = 0,
114 .n_row_addr = 15,
115 .n_col_addr = 10,
116 .n_banks_per_sdram_device = 8,
117 .edc_config = 0,
118 .burst_lengths_bitmask = 0x0c,
119
120 .tckmin_x_ps = 1071,
121 .caslat_x = 0xfe << 4, /* 5,6,7,8 */
122 .taa_ps = 13125,
123 .twr_ps = 15000,
124 .trcd_ps = 13125,
125 .trrd_ps = 7500,
126 .trp_ps = 13125,
127 .tras_ps = 37500,
128 .trc_ps = 50625,
129 .trfc_ps = 160000,
130 .twtr_ps = 7500,
131 .trtp_ps = 7500,
132 .refresh_rate_ps = 7800000,
133 .tfaw_ps = 37500,
134};
135
136int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
137 unsigned int controller_number,
138 unsigned int dimm_number)
139{
140 static const char dimm_model[] = "Fixed DDR on board";
141
142 if (((controller_number == 0) && (dimm_number == 0)) ||
143 ((controller_number == 1) && (dimm_number == 0))) {
144 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
145 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
146 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
147 }
148
149 return 0;
150}
151#endif
152
tang yuantian41ba57d2014-12-17 12:58:05 +0800153#if defined(CONFIG_DEEP_SLEEP)
154void board_mem_sleep_setup(void)
155{
156 void __iomem *qixis_base = (void *)QIXIS_BASE;
157
158 /* does not provide HW signals for power management */
159 clrbits_8(qixis_base + 0x21, 0x2);
160 udelay(1);
161}
162#endif
163
Wang Huan550e3dc2014-09-05 13:52:44 +0800164phys_size_t initdram(int board_type)
165{
166 phys_size_t dram_size;
167
Alison Wang86949c22014-12-03 15:00:47 +0800168#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
Wang Huan550e3dc2014-09-05 13:52:44 +0800169 puts("Initializing DDR....using SPD\n");
170 dram_size = fsl_ddr_sdram();
Alison Wang86949c22014-12-03 15:00:47 +0800171#else
172 dram_size = fsl_ddr_sdram_size();
173#endif
tang yuantian41ba57d2014-12-17 12:58:05 +0800174
175#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
176 fsl_dp_resume();
177#endif
178
Wang Huan550e3dc2014-09-05 13:52:44 +0800179 return dram_size;
180}
181
182void dram_init_banksize(void)
183{
184 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
185 gd->bd->bi_dram[0].size = gd->ram_size;
186}