blob: 42086197d9891b15e21b10eacc3efb988ffccc4f [file] [log] [blame]
Haikun.Wang@freescale.coma8919372015-03-24 22:03:58 +08001/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * Chao Fu (B44548@freescale.com)
8 * Haikun Wang (B53464@freescale.com)
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
Simon Glass4af0d7e2017-05-17 17:18:07 -060012
13#include <common.h>
Haikun.Wang@freescale.coma8919372015-03-24 22:03:58 +080014#include <dm.h>
15#include <errno.h>
16#include <common.h>
17#include <spi.h>
18#include <malloc.h>
19#include <asm/io.h>
20#include <fdtdec.h>
21#ifndef CONFIG_M68K
22#include <asm/arch/clock.h>
23#endif
24#include <fsl_dspi.h>
25
26DECLARE_GLOBAL_DATA_PTR;
27
28/* fsl_dspi_platdata flags */
Jagan Teki29e6abd2015-10-23 01:37:18 +053029#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
Haikun.Wang@freescale.coma8919372015-03-24 22:03:58 +080030
31/* idle data value */
32#define DSPI_IDLE_VAL 0x0
33
34/* max chipselect signals number */
35#define FSL_DSPI_MAX_CHIPSELECT 6
36
37/* default SCK frequency, unit: HZ */
38#define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
39
40/* tx/rx data wait timeout value, unit: us */
41#define DSPI_TXRX_WAIT_TIMEOUT 1000000
42
43/* CTAR register pre-configure value */
44#define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
45 DSPI_CTAR_PCSSCK_1CLK | \
46 DSPI_CTAR_PASC(0) | \
47 DSPI_CTAR_PDT(0) | \
48 DSPI_CTAR_CSSCK(0) | \
49 DSPI_CTAR_ASC(0) | \
50 DSPI_CTAR_DT(0))
51
52/* CTAR register pre-configure mask */
53#define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
54 DSPI_CTAR_PCSSCK(3) | \
55 DSPI_CTAR_PASC(3) | \
56 DSPI_CTAR_PDT(3) | \
57 DSPI_CTAR_CSSCK(15) | \
58 DSPI_CTAR_ASC(15) | \
59 DSPI_CTAR_DT(15))
60
61/**
62 * struct fsl_dspi_platdata - platform data for Freescale DSPI
63 *
64 * @flags: Flags for DSPI DSPI_FLAG_...
65 * @speed_hz: Default SCK frequency
66 * @num_chipselect: Number of DSPI chipselect signals
67 * @regs_addr: Base address of DSPI registers
68 */
69struct fsl_dspi_platdata {
70 uint flags;
71 uint speed_hz;
72 uint num_chipselect;
73 fdt_addr_t regs_addr;
74};
75
76/**
77 * struct fsl_dspi_priv - private data for Freescale DSPI
78 *
79 * @flags: Flags for DSPI DSPI_FLAG_...
80 * @mode: SPI mode to use for slave device (see SPI mode flags)
81 * @mcr_val: MCR register configure value
82 * @bus_clk: DSPI input clk frequency
83 * @speed_hz: Default SCK frequency
84 * @charbit: How many bits in every transfer
85 * @num_chipselect: Number of DSPI chipselect signals
86 * @ctar_val: CTAR register configure value of per chipselect slave device
87 * @regs: Point to DSPI register structure for I/O access
88 */
89struct fsl_dspi_priv {
90 uint flags;
91 uint mode;
92 uint mcr_val;
93 uint bus_clk;
94 uint speed_hz;
95 uint charbit;
96 uint num_chipselect;
97 uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
98 struct dspi *regs;
99};
100
101#ifndef CONFIG_DM_SPI
102struct fsl_dspi {
103 struct spi_slave slave;
104 struct fsl_dspi_priv priv;
105};
106#endif
107
108__weak void cpu_dspi_port_conf(void)
109{
110}
111
112__weak int cpu_dspi_claim_bus(uint bus, uint cs)
113{
114 return 0;
115}
116
117__weak void cpu_dspi_release_bus(uint bus, uint cs)
118{
119}
120
121static uint dspi_read32(uint flags, uint *addr)
122{
123 return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
124 in_be32(addr) : in_le32(addr);
125}
126
127static void dspi_write32(uint flags, uint *addr, uint val)
128{
129 flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
130 out_be32(addr, val) : out_le32(addr, val);
131}
132
133static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
134{
135 uint mcr_val;
136
137 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
138
139 if (halt)
140 mcr_val |= DSPI_MCR_HALT;
141 else
142 mcr_val &= ~DSPI_MCR_HALT;
143
144 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
145}
146
147static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
148{
149 /* halt DSPI module */
150 dspi_halt(priv, 1);
151
152 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
153
154 /* resume module */
155 dspi_halt(priv, 0);
156
157 priv->mcr_val = cfg_val;
158}
159
160static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
161 uint cs, uint state)
162{
163 uint mcr_val;
164
165 dspi_halt(priv, 1);
166
167 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
168 if (state & SPI_CS_HIGH)
169 /* CSx inactive state is low */
170 mcr_val &= ~DSPI_MCR_PCSIS(cs);
171 else
172 /* CSx inactive state is high */
173 mcr_val |= DSPI_MCR_PCSIS(cs);
174 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
175
176 dspi_halt(priv, 0);
177}
178
179static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
180 uint cs, uint mode)
181{
182 uint bus_setup;
183
184 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
185
186 bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
187 bus_setup |= priv->ctar_val[cs];
188 bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
189
190 if (mode & SPI_CPOL)
191 bus_setup |= DSPI_CTAR_CPOL;
192 if (mode & SPI_CPHA)
193 bus_setup |= DSPI_CTAR_CPHA;
194 if (mode & SPI_LSB_FIRST)
195 bus_setup |= DSPI_CTAR_LSBFE;
196
197 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
198
199 priv->charbit =
200 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
201 DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
202
203 return 0;
204}
205
206static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
207{
208 uint mcr_val;
209
210 dspi_halt(priv, 1);
211 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
212 /* flush RX and TX FIFO */
213 mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
214 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
215 dspi_halt(priv, 0);
216}
217
218static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
219{
220 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
221
222 /* wait for empty entries in TXFIFO or timeout */
223 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
224 timeout--)
225 udelay(1);
226
227 if (timeout >= 0)
228 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
229 else
230 debug("dspi_tx: waiting timeout!\n");
231}
232
233static u16 dspi_rx(struct fsl_dspi_priv *priv)
234{
235 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
236
237 /* wait for valid entries in RXFIFO or timeout */
238 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
239 timeout--)
240 udelay(1);
241
242 if (timeout >= 0)
243 return (u16)DSPI_RFR_RXDATA(
244 dspi_read32(priv->flags, &priv->regs->rfr));
245 else {
246 debug("dspi_rx: waiting timeout!\n");
247 return (u16)(~0);
248 }
249}
250
251static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
252 const void *dout, void *din, unsigned long flags)
253{
254 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
255 u8 *spi_rd = NULL, *spi_wr = NULL;
256 static u32 ctrl;
257 uint len = bitlen >> 3;
258
259 if (priv->charbit == 16) {
260 bitlen >>= 1;
261 spi_wr16 = (u16 *)dout;
262 spi_rd16 = (u16 *)din;
263 } else {
264 spi_wr = (u8 *)dout;
265 spi_rd = (u8 *)din;
266 }
267
268 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
269 ctrl |= DSPI_TFR_CONT;
270
271 ctrl = ctrl & DSPI_TFR_CONT;
272 ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
273
274 if (len > 1) {
275 int tmp_len = len - 1;
276 while (tmp_len--) {
277 if (dout != NULL) {
278 if (priv->charbit == 16)
279 dspi_tx(priv, ctrl, *spi_wr16++);
280 else
281 dspi_tx(priv, ctrl, *spi_wr++);
282 dspi_rx(priv);
283 }
284
285 if (din != NULL) {
286 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
287 if (priv->charbit == 16)
288 *spi_rd16++ = dspi_rx(priv);
289 else
290 *spi_rd++ = dspi_rx(priv);
291 }
292 }
293
294 len = 1; /* remaining byte */
295 }
296
297 if ((flags & SPI_XFER_END) == SPI_XFER_END)
298 ctrl &= ~DSPI_TFR_CONT;
299
300 if (len) {
301 if (dout != NULL) {
302 if (priv->charbit == 16)
303 dspi_tx(priv, ctrl, *spi_wr16);
304 else
305 dspi_tx(priv, ctrl, *spi_wr);
306 dspi_rx(priv);
307 }
308
309 if (din != NULL) {
310 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
311 if (priv->charbit == 16)
312 *spi_rd16 = dspi_rx(priv);
313 else
314 *spi_rd = dspi_rx(priv);
315 }
316 } else {
317 /* dummy read */
318 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
319 dspi_rx(priv);
320 }
321
322 return 0;
323}
324
325/**
326 * Calculate the divide value between input clk frequency and expected SCK frequency
327 * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
328 * Dbr: use default value 0
329 *
330 * @pbr: return Baud Rate Prescaler value
331 * @br: return Baud Rate Scaler value
332 * @speed_hz: expected SCK frequency
333 * @clkrate: input clk frequency
334 */
335static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
336 int speed_hz, uint clkrate)
337{
338 /* Valid baud rate pre-scaler values */
339 int pbr_tbl[4] = {2, 3, 5, 7};
340 int brs[16] = {2, 4, 6, 8,
341 16, 32, 64, 128,
342 256, 512, 1024, 2048,
343 4096, 8192, 16384, 32768};
344 int temp, i = 0, j = 0;
345
346 temp = clkrate / speed_hz;
347
348 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
349 for (j = 0; j < ARRAY_SIZE(brs); j++) {
350 if (pbr_tbl[i] * brs[j] >= temp) {
351 *pbr = i;
352 *br = j;
353 return 0;
354 }
355 }
356
357 debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
358 debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
359
360 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
361 *br = ARRAY_SIZE(brs) - 1;
362 return -EINVAL;
363}
364
365static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
366{
367 int ret;
368 uint bus_setup;
369 int best_i, best_j, bus_clk;
370
371 bus_clk = priv->bus_clk;
372
373 debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
374 speed, bus_clk);
375
376 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
377 bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
378
379 ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
380 if (ret) {
381 speed = priv->speed_hz;
382 debug("DSPI set_speed use default SCK rate %u.\n", speed);
383 fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
384 }
385
386 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
387 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
388
389 priv->speed_hz = speed;
390
391 return 0;
392}
393#ifndef CONFIG_DM_SPI
394void spi_init(void)
395{
396 /* Nothing to do */
397}
398
399void spi_init_f(void)
400{
401 /* Nothing to do */
402}
403
404void spi_init_r(void)
405{
406 /* Nothing to do */
407}
408
409int spi_cs_is_valid(unsigned int bus, unsigned int cs)
410{
411 if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
412 return 1;
413 else
414 return 0;
415}
416
417struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
418 unsigned int max_hz, unsigned int mode)
419{
420 struct fsl_dspi *dspi;
421 uint mcr_cfg_val;
422
423 dspi = spi_alloc_slave(struct fsl_dspi, bus, cs);
424 if (!dspi)
425 return NULL;
426
427 cpu_dspi_port_conf();
428
429#ifdef CONFIG_SYS_FSL_DSPI_BE
430 dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
431#endif
432
433 dspi->priv.regs = (struct dspi *)MMAP_DSPI;
434
435#ifdef CONFIG_M68K
436 dspi->priv.bus_clk = gd->bus_clk;
437#else
438 dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK);
439#endif
440 dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ;
441
442 /* default: all CS signals inactive state is high */
443 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
444 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
445 fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val);
446
447 for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++)
448 dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE;
449
450#ifdef CONFIG_SYS_DSPI_CTAR0
451 if (FSL_DSPI_MAX_CHIPSELECT > 0)
452 dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0;
453#endif
454#ifdef CONFIG_SYS_DSPI_CTAR1
455 if (FSL_DSPI_MAX_CHIPSELECT > 1)
456 dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1;
457#endif
458#ifdef CONFIG_SYS_DSPI_CTAR2
459 if (FSL_DSPI_MAX_CHIPSELECT > 2)
460 dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2;
461#endif
462#ifdef CONFIG_SYS_DSPI_CTAR3
463 if (FSL_DSPI_MAX_CHIPSELECT > 3)
464 dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3;
465#endif
466#ifdef CONFIG_SYS_DSPI_CTAR4
467 if (FSL_DSPI_MAX_CHIPSELECT > 4)
468 dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4;
469#endif
470#ifdef CONFIG_SYS_DSPI_CTAR5
471 if (FSL_DSPI_MAX_CHIPSELECT > 5)
472 dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5;
473#endif
474#ifdef CONFIG_SYS_DSPI_CTAR6
475 if (FSL_DSPI_MAX_CHIPSELECT > 6)
476 dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6;
477#endif
478#ifdef CONFIG_SYS_DSPI_CTAR7
479 if (FSL_DSPI_MAX_CHIPSELECT > 7)
480 dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7;
481#endif
482
483 fsl_dspi_cfg_speed(&dspi->priv, max_hz);
484
485 /* configure transfer mode */
486 fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode);
487
488 /* configure active state of CSX */
489 fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode);
490
491 return &dspi->slave;
492}
493
494void spi_free_slave(struct spi_slave *slave)
495{
496 free(slave);
497}
498
499int spi_claim_bus(struct spi_slave *slave)
500{
501 uint sr_val;
502 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
503
504 cpu_dspi_claim_bus(slave->bus, slave->cs);
505
506 fsl_dspi_clr_fifo(&dspi->priv);
507
508 /* check module TX and RX status */
509 sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr);
510 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
511 debug("DSPI RX/TX not ready!\n");
512 return -EIO;
513 }
514
515 return 0;
516}
517
518void spi_release_bus(struct spi_slave *slave)
519{
520 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
521
522 dspi_halt(&dspi->priv, 1);
523 cpu_dspi_release_bus(slave->bus.slave->cs);
524}
525
526int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
527 void *din, unsigned long flags)
528{
529 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
530 return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags);
531}
532#else
533static int fsl_dspi_child_pre_probe(struct udevice *dev)
534{
535 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
536 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
537
538 if (slave_plat->cs >= priv->num_chipselect) {
539 debug("DSPI invalid chipselect number %d(max %d)!\n",
540 slave_plat->cs, priv->num_chipselect - 1);
541 return -EINVAL;
542 }
543
544 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
545
546 debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
547 slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
548
549 return 0;
550}
551
552static int fsl_dspi_probe(struct udevice *bus)
553{
554 struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
555 struct fsl_dspi_priv *priv = dev_get_priv(bus);
556 struct dm_spi_bus *dm_spi_bus;
557 uint mcr_cfg_val;
558
559 dm_spi_bus = bus->uclass_priv;
560
561 /* cpu speical pin muxing configure */
562 cpu_dspi_port_conf();
563
564 /* get input clk frequency */
565 priv->regs = (struct dspi *)plat->regs_addr;
566 priv->flags = plat->flags;
567#ifdef CONFIG_M68K
568 priv->bus_clk = gd->bus_clk;
569#else
570 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
571#endif
572 priv->num_chipselect = plat->num_chipselect;
573 priv->speed_hz = plat->speed_hz;
574 /* frame data length in bits, default 8bits */
575 priv->charbit = 8;
576
577 dm_spi_bus->max_hz = plat->speed_hz;
578
579 /* default: all CS signals inactive state is high */
580 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
581 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
582 fsl_dspi_init_mcr(priv, mcr_cfg_val);
583
584 debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
585
586 return 0;
587}
588
589static int fsl_dspi_claim_bus(struct udevice *dev)
590{
591 uint sr_val;
592 struct fsl_dspi_priv *priv;
593 struct udevice *bus = dev->parent;
594 struct dm_spi_slave_platdata *slave_plat =
595 dev_get_parent_platdata(dev);
596
597 priv = dev_get_priv(bus);
598
Robert P. J. Dayfc0b5942016-09-07 14:27:59 -0400599 /* processor special preparation work */
Haikun.Wang@freescale.coma8919372015-03-24 22:03:58 +0800600 cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
601
602 /* configure transfer mode */
603 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
604
605 /* configure active state of CSX */
606 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
607 priv->mode);
608
609 fsl_dspi_clr_fifo(priv);
610
611 /* check module TX and RX status */
612 sr_val = dspi_read32(priv->flags, &priv->regs->sr);
613 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
614 debug("DSPI RX/TX not ready!\n");
615 return -EIO;
616 }
617
618 return 0;
619}
620
621static int fsl_dspi_release_bus(struct udevice *dev)
622{
623 struct udevice *bus = dev->parent;
624 struct fsl_dspi_priv *priv = dev_get_priv(bus);
625 struct dm_spi_slave_platdata *slave_plat =
626 dev_get_parent_platdata(dev);
627
628 /* halt module */
629 dspi_halt(priv, 1);
630
631 /* processor special release work */
632 cpu_dspi_release_bus(bus->seq, slave_plat->cs);
633
634 return 0;
635}
636
637/**
638 * This function doesn't do anything except help with debugging
639 */
640static int fsl_dspi_bind(struct udevice *bus)
641{
642 debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq);
643 return 0;
644}
645
646static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
647{
648 fdt_addr_t addr;
649 struct fsl_dspi_platdata *plat = bus->platdata;
650 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700651 int node = dev_of_offset(bus);
Haikun.Wang@freescale.coma8919372015-03-24 22:03:58 +0800652
653 if (fdtdec_get_bool(blob, node, "big-endian"))
654 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
655
656 plat->num_chipselect =
657 fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
658
Simon Glassa821c4a2017-05-17 17:18:05 -0600659 addr = devfdt_get_addr(bus);
Haikun.Wang@freescale.coma8919372015-03-24 22:03:58 +0800660 if (addr == FDT_ADDR_T_NONE) {
661 debug("DSPI: Can't get base address or size\n");
662 return -ENOMEM;
663 }
664 plat->regs_addr = addr;
665
666 plat->speed_hz = fdtdec_get_int(blob,
667 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
668
York Sunfdb9f342015-08-03 12:02:05 -0700669 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
670 &plat->regs_addr, plat->speed_hz,
Haikun.Wang@freescale.coma8919372015-03-24 22:03:58 +0800671 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
672 plat->num_chipselect);
673
674 return 0;
675}
676
677static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
678 const void *dout, void *din, unsigned long flags)
679{
680 struct fsl_dspi_priv *priv;
681 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
682 struct udevice *bus;
683
684 bus = dev->parent;
685 priv = dev_get_priv(bus);
686
687 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
688}
689
690static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
691{
692 struct fsl_dspi_priv *priv = dev_get_priv(bus);
693
694 return fsl_dspi_cfg_speed(priv, speed);
695}
696
697static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
698{
699 struct fsl_dspi_priv *priv = dev_get_priv(bus);
700
701 debug("DSPI set_mode: mode 0x%x.\n", mode);
702
703 /*
704 * We store some chipselect special configure value in priv->ctar_val,
705 * and we can't get the correct chipselect number here,
706 * so just store mode value.
707 * Do really configuration when claim_bus.
708 */
709 priv->mode = mode;
710
711 return 0;
712}
713
714static const struct dm_spi_ops fsl_dspi_ops = {
715 .claim_bus = fsl_dspi_claim_bus,
716 .release_bus = fsl_dspi_release_bus,
717 .xfer = fsl_dspi_xfer,
718 .set_speed = fsl_dspi_set_speed,
719 .set_mode = fsl_dspi_set_mode,
720};
721
722static const struct udevice_id fsl_dspi_ids[] = {
723 { .compatible = "fsl,vf610-dspi" },
724 { }
725};
726
727U_BOOT_DRIVER(fsl_dspi) = {
728 .name = "fsl_dspi",
729 .id = UCLASS_SPI,
730 .of_match = fsl_dspi_ids,
731 .ops = &fsl_dspi_ops,
732 .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata,
733 .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata),
734 .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv),
735 .probe = fsl_dspi_probe,
736 .child_pre_probe = fsl_dspi_child_pre_probe,
737 .bind = fsl_dspi_bind,
738};
739#endif