blob: b90e047955b909f26c4c2e6000d3c561288a9f12 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +01002/*
3 * (C) Copyright 2007-2013
4 * Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Lead Tech Design <www.leadtechdesign.com>
6 * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
7 * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
8 *
9 * Settings for Calao USB-A9263 board
10 *
11 * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap
12 * installed on board will not be able to load it properly.
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17#include <asm/hardware.h>
18
19/* ARM asynchronous clock */
Tom Rini65cc0e22022-11-16 13:10:41 -050020#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
21#define CFG_SYS_AT91_SLOW_CLOCK 32768
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010022
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010023/*
24 * Hardware drivers
25 */
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010026
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010027/* SDRAM */
Tom Riniaa6e94d2022-11-16 13:10:37 -050028#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
29#define CFG_SYS_SDRAM_SIZE 0x04000000
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010030
Tom Rini65cc0e22022-11-16 13:10:41 -050031#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
32#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010033
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010034/* NAND flash */
35#ifdef CONFIG_CMD_NAND
Tom Rini4e590942022-11-12 17:36:51 -050036#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010037/* our ALE is AD21 */
Tom Rini4e590942022-11-12 17:36:51 -050038#define CFG_SYS_NAND_MASK_ALE (1 << 21)
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010039/* our CLE is AD22 */
Tom Rini4e590942022-11-12 17:36:51 -050040#define CFG_SYS_NAND_MASK_CLE (1 << 22)
41#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
42#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010043#endif
44
Wenyou.Yang@microchip.comfdc77182017-07-21 17:07:46 +080045/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Tom Rini0613c362022-12-04 10:03:50 -050046#define CFG_EXTRA_ENV_SETTINGS \
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010047
Mateusz Kulikowski1dcdd862013-12-02 23:30:58 +010048#endif