src/arm64/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 *
 * This file defines the common audio settings for the child boards
 * using rt5682 codec and having 3 dmics connected to sc7280.
 *
 * Copyright 2022 Google LLC.
 */

/ {
	/* BOARD-SPECIFIC TOP LEVEL NODES */
	sound: sound {
		compatible = "google,sc7280-herobrine";
		model = "sc7280-rt5682-max98360a-3mic";

		audio-routing = "VA DMIC0", "vdd-micb",
				"VA DMIC1", "vdd-micb",
				"VA DMIC2", "vdd-micb",
				"VA DMIC3", "vdd-micb",

				"Headphone Jack", "HPOL",
				"Headphone Jack", "HPOR";

		#address-cells = <1>;
		#size-cells = <0>;

		dai-link@0 {
			link-name = "MAX98360";
			reg = <0>;

			cpu {
				sound-dai = <&lpass_cpu MI2S_SECONDARY>;
			};

			codec {
				sound-dai = <&max98360a>;
			};
		};

		dai-link@1 {
			link-name = "DisplayPort";
			reg = <1>;

			cpu {
				sound-dai = <&lpass_cpu LPASS_DP_RX>;
			};

			codec {
				sound-dai = <&mdss_dp>;
			};
		};

		dai-link@2 {
			link-name = "ALC5682";
			reg = <2>;

			cpu {
				sound-dai = <&lpass_cpu MI2S_PRIMARY>;
			};

			codec {
				sound-dai = <&alc5682 0 /* aif1 */>;
			};
		};

		dai-link@4 {
			link-name = "DMIC";
			reg = <4>;

			cpu {
				sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
			};

			codec {
				sound-dai = <&lpass_va_macro 0>;
			};
		};
	};
};

hp_i2c: &i2c2 {
	clock-frequency = <400000>;
	status = "okay";

	alc5682: codec@1a {
		compatible = "realtek,rt5682s";
		reg = <0x1a>;
		pinctrl-names = "default";
		pinctrl-0 = <&hp_irq>;

		#sound-dai-cells = <1>;

		interrupt-parent = <&tlmm>;
		interrupts = <101 IRQ_TYPE_EDGE_BOTH>;

		AVDD-supply = <&pp1800_alc5682>;
		DBVDD-supply = <&pp1800_alc5682>;
		LDO1-IN-supply = <&pp1800_alc5682>;
		MICVDD-supply = <&pp3300_codec>;

		realtek,dmic1-data-pin = <1>;
		realtek,dmic1-clk-pin = <2>;
		realtek,jd-src = <1>;
		realtek,dmic-clk-rate-hz = <2048000>;
	};
};

&lpass_cpu {
	pinctrl-names = "default";
	pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
			<&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;

	#address-cells = <1>;
	#size-cells = <0>;

	status = "okay";

	dai-link@0 {
		reg = <MI2S_PRIMARY>;
		qcom,playback-sd-lines = <1>;
		qcom,capture-sd-lines = <0>;
	};

	dai-link@1 {
		reg = <MI2S_SECONDARY>;
		qcom,playback-sd-lines = <0>;
	};

	dai-link@5 {
		reg = <LPASS_DP_RX>;
	};

	dai-link@25 {
		reg = <LPASS_CDC_DMA_VA_TX0>;
	};
};

&lpass_va_macro {
	vdd-micb-supply = <&pp1800_l2c>;
	pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, <&lpass_dmic23_clk>,
			<&lpass_dmic23_data>;

	status = "okay";
};

/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */

&lpass_dmic01_clk {
	drive-strength = <8>;
	bias-disable;
};

&lpass_dmic01_data {
	bias-pull-down;
};

&lpass_dmic23_clk {
	drive-strength = <8>;
	bias-disable;
};

&lpass_dmic23_data {
	bias-pull-down;
};

&mi2s0_data0 {
	drive-strength = <6>;
	bias-disable;
};

&mi2s0_data1 {
	drive-strength = <6>;
	bias-disable;
};

&mi2s0_mclk {
	drive-strength = <6>;
	bias-disable;
};

&mi2s0_sclk {
	drive-strength = <6>;
	bias-disable;
};

&mi2s0_ws {
	drive-strength = <6>;
	bias-disable;
};