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Michael Wallef214a202012-06-05 11:33:17 +00001#
2# Copyright (c) 2012 Michael Walle
3# Michael Walle <michael@walle.cc>
4#
5# See file CREDITS for list of people who contributed to this
6# project.
7#
8# This program is free software; you can redistribute it and/or
9# modify it under the terms of the GNU General Public License as
10# published by the Free Software Foundation; either version 2 of
11# the License, or (at your option) any later version.
12#
13# This program is distributed in the hope that it will be useful,
14# but WITHOUT ANY WARRANTY; without even the implied warranty of
15# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16# GNU General Public License for more details.
17#
18# You should have received a copy of the GNU General Public License
19# along with this program; if not, write to the Free Software
20# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21# MA 02110-1301 USA
22#
Anatolij Gustschinb1e6c4c2013-04-30 11:15:33 +000023# Refer doc/README.kwbimage for more details about how-to configure
Michael Wallef214a202012-06-05 11:33:17 +000024# and create kirkwood boot image
25#
26
27# Boot Media configurations
28BOOT_FROM spi
29
30# SOC registers configuration using bootrom header extension
31# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
32
33# Configure RGMII-0/1 interface pad voltage to 1.8V
34DATA 0xFFD100E0 0x1B1B1B9B
35
36# L2 RAM Timing 0
37DATA 0xFFD20134 0xBBBBBBBB
38# not further specified in HW manual, timing taken from original vendor port
39
40# L2 RAM Timing 1
41DATA 0xFFD20138 0x00BBBBBB
42# not further specified in HW manual, timing taken from original vendor port
43
44# DDR Configuration register
45DATA 0xFFD01400 0x43000618
46# bit13-0: 0x618, 1560 DDR2 clks refresh rate
47# bit23-14: 0 required
48# bit24: 1, enable exit self refresh mode on DDR access
49# bit25: 1 required
50# bit29-26: 0 required
51# bit31-30: 0b01 required
52
53# DDR Controller Control Low
54DATA 0xFFD01404 0x39543000
55# bit3-0: 0 required
56# bit4: 0, addr/cmd in same cycle
57# bit5: 0, clk is driven during self refresh, we don't care for APX
58# bit6: 0, use recommended falling edge of clk for addr/cmd
59# bit11-7: 0 required
60# bit12: 1 required
61# bit13: 1 required
62# bit14: 0, input buffer always powered up
63# bit17-15: 0 required
64# bit18: 1, cpu lock transaction enabled
65# bit19: 0 required
66# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
67# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
68# bit30-28: 3 required
69# bit31: 0, no additional STARTBURST delay
70
71# DDR Timing (Low)
72DATA 0xFFD01408 0x3302444F
73# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
74# bit7-4: 4, 5 cycle tRCD
75# bit11-8: 4, 5 cyle tRP
76# bit15-12: 4, 5 cyle tWR
77# bit19-16: 2, 3 cyle tWTR
78# bit20: 0, 16 cycle tRAS (tRAS[4])
79# bit23-21: 0 required
80# bit27-24: 3, 4 cycle tRRD
81# bit31-28: 3, 4 cyle tRTP
82
83# DDR Timing (High)
84DATA 0xFFD0140C 0x00000823
85# bit6-0: 0x23, 35 cycle tRFC
86# bit8-7: 0, 1 cycle tR2R
87# bit10-9: 0, 1 cyle tR2W
88# bit12-11: 1, 2 cylce tW2W
89# bit31-13: 0 required
90
91# DDR Address Control
92DATA 0xFFD01410 0x00000009
93# bit1-0: 1, Cs0width=x16
94# bit3-2: 2, Cs0size=512Mbit
95# bit5-4: 0, Cs1width=nonexistent
96# bit7-6: 0, Cs1size=nonexistent
97# bit9-8: 0, Cs2width=nonexistent
98# bit11-10: 0, Cs2size=nonexistent
99# bit13-12: 0, Cs3width=nonexistent
100# bit15-14: 0, Cs3size=nonexistent
101# bit16: 0, Cs0AddrSel
102# bit17: 0, Cs1AddrSel
103# bit18: 0, Cs2AddrSel
104# bit19: 0, Cs3AddrSel
105# bit31-20: 0 required
106
107# DDR Open Pages Control
108DATA 0xFFD01414 0x00000000
109# bit0: 0, OPEn=OpenPage enabled
110# bit31-1: 0 required
111
112# DDR Operation
113DATA 0xFFD01418 0x00000000
114# bit3-0: 0, Cmd=Normal SDRAM Mode
115# bit31-4: 0 required
116
117# DDR Mode
118DATA 0xFFD0141C 0x00000652
119# bit2-0: 2, Burst Length (2 required)
120# bit3: 0, Burst Type (0 required)
121# bit6-4: 5, CAS Latency (CL) 5
122# bit7: 0, (Test Mode) Normal operation
123# bit8: 0, (Reset DLL) Normal operation
124# bit11-9: 3, Write recovery for auto-precharge (3 required)
125# bit12: 0, Fast Active power down exit time (0 required)
126# bit31-13: 0 required
127
128# DDR Extended Mode
129DATA 0xFFD01420 0x00000042
130# bit0: 0, DRAM DLL enabled
131# bit1: 1, DRAM drive strength reduced
132# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
133# bit5-3: 0 required
134# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
135# bit9-7: 0 required
136# bit10: 0, differential DQS enabled
137# bit11: 0 required
138# bit12: 0, DRAM output buffer enabled
139# bit31-13: 0 required
140
141# DDR Controller Control High
142DATA 0xFFD01424 0x0000F17F
143# bit2-0: 0x7 required
144# bit3: 1, MBUS Burst Chop disabled
145# bit6-4: 0x7 required
146# bit7: 0 required (???)
147# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
148# bit9: 0, no half clock cycle addition to dataout
149# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
150# bit11: 0, 1/4 clock cycle skew disabled for write mesh
151# bit15-12: 0xf required
152# bit31-16: 0 required
153
154# DDR2 ODT Read Timing (default values)
155DATA 0xFFD01428 0x00085520
156# bit3-0: 0 required
157# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
158# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
159# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
160# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
161# bit31-20: 0 required
162
163# DDR2 ODT Write Timing (default values)
164DATA 0xFFD0147C 0x00008552
165# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
166# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
167# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
168# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
169# bit31-16: 0 required
170
171# CS[0]n Base address
172DATA 0xFFD01500 0x00000000
173# at 0x0
174
175# CS[0]n Size
176DATA 0xFFD01504 0x03FFFFF1
177# bit0: 1, Window enabled
178# bit1: 0, Write Protect disabled
179# bit3-2: 0x0, CS0 hit selected
180# bit23-4: 0xfffff required
181# bit31-24: 0x03, Size (i.e. 64MB)
182
183# CS[1]n Size
184DATA 0xFFD0150C 0x00000000
185# window disabled
186
187# CS[2]n Size
188DATA 0xFFD01514 0x00000000
189# window disabled
190
191# CS[3]n Size
192DATA 0xFFD0151C 0x00000000
193# window disabled
194
195# DDR ODT Control (Low)
196DATA 0xFFD01494 0x003C0000
197# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
198# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
199# bit15-8: 0 required
200# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
201# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
202# bit31-24: 0 required
203
204# DDR ODT Control (High)
205DATA 0xFFD01498 0x00000000
206# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
207# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
208# bit31-4 0 required
209
210# CPU ODT Control
211DATA 0xFFD0149C 0x0000E80F
212# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
213# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
214# bit9-8: 0, Internal ODT assertion is controlled by fiels
215# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
216# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
217# bit14: 1, M_STARTBURST_IN ODT enabled
218# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
219# bit20-16: 0, Pad N channel driving strength for ODT
220# bit25-21: 0, Pad P channel driving strength for ODT
221# bit31-26: 0 required
222
223# DDR Initialization Control
224DATA 0xFFD01480 0x00000001
225# bit0: 1, enable DDR init upon this register write
226# bit31-1: 0, required
227
228# End of Header extension
229DATA 0x0 0x0