blob: eb8e567554c8840bdfb14d2dce541621692dcbd9 [file] [log] [blame]
Ying Zhangc9e1f582014-01-24 15:50:09 +08001/* Copyright 2013 Freescale Semiconductor, Inc.
2 *
3 * SPDX-License-Identifier: GPL-2.0+
4 */
5
6#include <common.h>
Simon Glass24b852a2015-11-08 23:47:45 -07007#include <console.h>
Ying Zhangc9e1f582014-01-24 15:50:09 +08008#include <ns16550.h>
9#include <malloc.h>
10#include <mmc.h>
11#include <nand.h>
12#include <i2c.h>
13#include <fsl_esdhc.h>
14#include <spi_flash.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
Tom Rinia7e8c152014-02-25 12:44:13 -050018phys_size_t get_effective_memsize(void)
Ying Zhangc9e1f582014-01-24 15:50:09 +080019{
20 return CONFIG_SYS_L2_SIZE;
21}
22
23void board_init_f(ulong bootflag)
24{
25 u32 plat_ratio;
26 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -070027 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
Ying Zhangc9e1f582014-01-24 15:50:09 +080028
29 console_init_f();
30
31 /* Clock configuration to access CPLD using IFC(GPCM) */
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -070032 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
Ying Zhangc9e1f582014-01-24 15:50:09 +080033
34#ifdef CONFIG_P1010RDB_PB
35 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
36#endif
37
38 /* initialize selected port with appropriate baud rate */
39 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
40 plat_ratio >>= 1;
41 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
42
43 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
44 gd->bus_clk / 16 / CONFIG_BAUDRATE);
45
46#ifdef CONFIG_SPL_MMC_BOOT
47 puts("\nSD boot...\n");
48#elif defined(CONFIG_SPL_SPI_BOOT)
49 puts("\nSPI Flash boot...\n");
50#endif
51 /* copy code to RAM and jump to it - this should not return */
52 /* NOTE - code has to be copied out of NAND buffer before
53 * other blocks can be read.
54 */
55 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
56}
57
58void board_init_r(gd_t *gd, ulong dest_addr)
59{
60 /* Pointer is writable since we allocated a register for it */
61 gd = (gd_t *)CONFIG_SPL_GD_ADDR;
62 bd_t *bd;
63
64 memset(gd, 0, sizeof(gd_t));
65 bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
66 memset(bd, 0, sizeof(bd_t));
67 gd->bd = bd;
68 bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
69 bd->bi_memsize = CONFIG_SYS_L2_SIZE;
70
71 probecpu();
72 get_clocks();
73 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
74 CONFIG_SPL_RELOC_MALLOC_SIZE);
75
76#ifndef CONFIG_SPL_NAND_BOOT
77 env_init();
78#endif
79#ifdef CONFIG_SPL_MMC_BOOT
80 mmc_initialize(bd);
81#endif
82
83 /* relocate environment function pointers etc. */
84#ifdef CONFIG_SPL_NAND_BOOT
85 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
86 (uchar *)CONFIG_ENV_ADDR);
87 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
88 gd->env_valid = 1;
89#else
90 env_relocate();
91#endif
92
93 i2c_init_all();
94
95 gd->ram_size = initdram(0);
96#ifdef CONFIG_SPL_NAND_BOOT
97 puts("\nTertiary program loader running in sram...");
98#else
99 puts("\nSecond program loader running in sram...");
100#endif
101
102#ifdef CONFIG_SPL_MMC_BOOT
103 mmc_boot();
104#elif defined(CONFIG_SPL_SPI_BOOT)
105 spi_boot();
106#elif defined(CONFIG_SPL_NAND_BOOT)
107 nand_boot();
108#endif
109}