blob: 52f3ea167f1b1f4afd582be8ec356ee9f65f583c [file] [log] [blame]
Dirk Eibachb9944a72013-06-26 15:55:17 +02001/*
2 * (C) Copyright 2012
3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4 *
Tom Rini9fab4bf2013-07-26 15:32:59 -04005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibachb9944a72013-06-26 15:55:17 +02006 */
7
8/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
9
10#include <common.h>
11#include <asm/io.h>
12#include <errno.h>
13#include <i2c.h>
14
15static void dp501_setbits(u8 addr, u8 reg, u8 mask)
16{
17 u8 val;
18
19 val = i2c_reg_read(addr, reg);
20 setbits_8(&val, mask);
21 i2c_reg_write(addr, reg, val);
22}
23
24static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
25{
26 u8 val;
27
28 val = i2c_reg_read(addr, reg);
29 clrbits_8(&val, mask);
30 i2c_reg_write(addr, reg, val);
31}
32
33static int dp501_detect_cable_adapter(u8 addr)
34{
35 u8 val = i2c_reg_read(addr, 0x00);
36
37 return !(val & 0x04);
38}
39
40static void dp501_link_training(u8 addr)
41{
42 u8 val;
43
44 val = i2c_reg_read(addr, 0x51);
45 i2c_reg_write(addr, 0x5d, val); /* set link_bw */
46 val = i2c_reg_read(addr, 0x52);
47 i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */
48 val = i2c_reg_read(addr, 0x53);
49 i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
50
51 i2c_reg_write(addr, 0x5f, 0x0d); /* start training */
52}
53
54void dp501_powerup(u8 addr)
55{
56 dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
57 i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
58 dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
59 dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
60 i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
61 dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
62 dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
63 i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
64 i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
65
66 if (dp501_detect_cable_adapter(addr)) {
67 printf("DVI/HDMI cable adapter detected\n");
68 i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */
69 dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
70 } else {
71 printf("no DVI/HDMI cable adapter detected\n");
72 i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
73 i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
74 i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
75 i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
76 i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
77 i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
78 dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
79 i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
80 i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
81 i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
82 dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
83
84 dp501_link_training(addr);
85 }
86}
87
88void dp501_powerdown(u8 addr)
89{
90 dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
91}