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wdenkc6097192002-11-03 00:24:07 +00001/*
stroese6f4474e2003-03-20 15:31:19 +00002 * (C) Copyright 2001-2003
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
wdenkc6097192002-11-03 00:24:07 +000027#include <malloc.h>
28
29/* ------------------------------------------------------------------------- */
wdenk8bde7f72003-06-27 21:31:46 +000030extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
wdenkc6097192002-11-03 00:24:07 +000031#if 0
32#define FPGA_DEBUG
33#endif
34
35/* fpga configuration data - generated by bin2cc */
36const unsigned char fpgadata[] =
37{
38#ifdef CONFIG_CPCI405_VER2
stroesed4629c82003-05-23 11:30:39 +000039# ifdef CONFIG_CPCI405AB
40# include "fpgadata_cpci405ab.c"
41# else
42# include "fpgadata_cpci4052.c"
43# endif
wdenkc6097192002-11-03 00:24:07 +000044#else
45# include "fpgadata_cpci405.c"
46#endif
47};
48
49/*
50 * include common fpga code (for esd boards)
51 */
52#include "../common/fpga.c"
53
54
55/* Prototypes */
stroese6f4474e2003-03-20 15:31:19 +000056int cpci405_version(void);
wdenkc6097192002-11-03 00:24:07 +000057int gunzip(void *, int, unsigned char *, int *);
58
59
wdenkc837dcb2004-01-20 23:12:12 +000060int board_early_init_f (void)
wdenkc6097192002-11-03 00:24:07 +000061{
62#ifndef CONFIG_CPCI405_VER2
63 int index, len, i;
64 int status;
65#endif
66
67#ifdef FPGA_DEBUG
68 DECLARE_GLOBAL_DATA_PTR;
69
70 /* set up serial port with default baudrate */
71 (void) get_clocks ();
72 gd->baudrate = CONFIG_BAUDRATE;
73 serial_init ();
74 console_init_f();
75#endif
76
77 /*
78 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
79 */
stroesed4629c82003-05-23 11:30:39 +000080 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
81 out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
82 out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
83 out32(GPIO0_OR, 0); /* pull prg low */
wdenkc6097192002-11-03 00:24:07 +000084
85 /*
86 * Boot onboard FPGA
87 */
88#ifndef CONFIG_CPCI405_VER2
stroese6f4474e2003-03-20 15:31:19 +000089 if (cpci405_version() == 1) {
wdenkc6097192002-11-03 00:24:07 +000090 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
91 if (status != 0) {
92 /* booting FPGA failed */
93#ifndef FPGA_DEBUG
94 DECLARE_GLOBAL_DATA_PTR;
95
96 /* set up serial port with default baudrate */
97 (void) get_clocks ();
98 gd->baudrate = CONFIG_BAUDRATE;
99 serial_init ();
100 console_init_f();
101#endif
102 printf("\nFPGA: Booting failed ");
103 switch (status) {
104 case ERROR_FPGA_PRG_INIT_LOW:
105 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
106 break;
107 case ERROR_FPGA_PRG_INIT_HIGH:
108 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
109 break;
110 case ERROR_FPGA_PRG_DONE:
111 printf("(Timeout: DONE not high after programming FPGA)\n ");
112 break;
113 }
114
115 /* display infos on fpgaimage */
116 index = 15;
117 for (i=0; i<4; i++) {
118 len = fpgadata[index];
119 printf("FPGA: %s\n", &(fpgadata[index+1]));
120 index += len+3;
121 }
122 putc ('\n');
123 /* delayed reboot */
124 for (i=20; i>0; i--) {
125 printf("Rebooting in %2d seconds \r",i);
126 for (index=0;index<1000;index++)
127 udelay(1000);
128 }
129 putc ('\n');
130 do_reset(NULL, 0, 0, NULL);
131 }
132 }
133#endif /* !CONFIG_CPCI405_VER2 */
134
135 /*
136 * IRQ 0-15 405GP internally generated; active high; level sensitive
137 * IRQ 16 405GP internally generated; active low; level sensitive
138 * IRQ 17-24 RESERVED
139 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
140 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
141 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
142 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
143 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
144 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
145 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
146 */
147 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
148 mtdcr(uicer, 0x00000000); /* disable all ints */
149 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
stroese6f4474e2003-03-20 15:31:19 +0000150 if (cpci405_version() == 3) {
151 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
152 } else {
153 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
154 }
wdenkc6097192002-11-03 00:24:07 +0000155 mtdcr(uictr, 0x10000000); /* set int trigger levels */
156 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
157 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
158
159 return 0;
160}
161
162
163/* ------------------------------------------------------------------------- */
164
165int ctermm2(void)
166{
167#ifdef CONFIG_CPCI405_VER2
168 return 0; /* no, board is cpci405 */
169#else
170 if ((*(unsigned char *)0xf0000400 == 0x00) &&
171 (*(unsigned char *)0xf0000401 == 0x01))
172 return 0; /* no, board is cpci405 */
173 else
174 return -1; /* yes, board is cterm-m2 */
175#endif
176}
177
178
179int cpci405_host(void)
180{
181 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
182 return -1; /* yes, board is cpci405 host */
183 else
184 return 0; /* no, board is cpci405 adapter */
185}
186
187
stroese6f4474e2003-03-20 15:31:19 +0000188int cpci405_version(void)
wdenkc6097192002-11-03 00:24:07 +0000189{
190 unsigned long cntrl0Reg;
191 unsigned long value;
192
193 /*
stroese6f4474e2003-03-20 15:31:19 +0000194 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
wdenkc6097192002-11-03 00:24:07 +0000195 */
196 cntrl0Reg = mfdcr(cntrl0);
stroese6f4474e2003-03-20 15:31:19 +0000197 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
stroesed4629c82003-05-23 11:30:39 +0000198 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
199 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
wdenkc6097192002-11-03 00:24:07 +0000200 udelay(1000); /* wait some time before reading input */
stroesed4629c82003-05-23 11:30:39 +0000201 value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
wdenkc6097192002-11-03 00:24:07 +0000202
203 /*
stroese6f4474e2003-03-20 15:31:19 +0000204 * Restore GPIO settings
wdenkc6097192002-11-03 00:24:07 +0000205 */
206 mtdcr(cntrl0, cntrl0Reg);
207
stroese6f4474e2003-03-20 15:31:19 +0000208 switch (value) {
209 case 0x00180000:
210 /* CS2==1 && CS3==1 -> version 1 */
211 return 1;
212 case 0x00080000:
213 /* CS2==0 && CS3==1 -> version 2 */
214 return 2;
215 case 0x00100000:
216 /* CS2==1 && CS3==0 -> version 3 */
217 return 3;
218 case 0x00000000:
219 /* CS2==0 && CS3==0 -> version 4 */
220 return 4;
221 default:
222 /* should not be reached! */
223 return 2;
224 }
wdenkc6097192002-11-03 00:24:07 +0000225}
226
227
228int misc_init_f (void)
229{
230 return 0; /* dummy implementation */
231}
232
233
234int misc_init_r (void)
235{
236 DECLARE_GLOBAL_DATA_PTR;
237
238 bd_t *bd = gd->bd;
239 char * tmp; /* Temporary char pointer */
stroeseafcc4a72003-04-04 16:52:57 +0000240 unsigned long cntrl0Reg;
wdenkc6097192002-11-03 00:24:07 +0000241
242#ifdef CONFIG_CPCI405_VER2
243 unsigned char *dst;
244 ulong len = sizeof(fpgadata);
245 int status;
246 int index;
247 int i;
wdenkc6097192002-11-03 00:24:07 +0000248
249 /*
250 * On CPCI-405 version 2 the environment is saved in eeprom!
251 * FPGA can be gzip compressed (malloc) and booted this late.
252 */
253
stroese6f4474e2003-03-20 15:31:19 +0000254 if (cpci405_version() >= 2) {
wdenkc6097192002-11-03 00:24:07 +0000255 /*
256 * Setup GPIO pins (CS6+CS7 as GPIO)
257 */
258 cntrl0Reg = mfdcr(cntrl0);
259 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
260
261 dst = malloc(CFG_FPGA_MAX_SIZE);
262 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
263 printf ("GUNZIP ERROR - must RESET board to recover\n");
264 do_reset (NULL, 0, 0, NULL);
265 }
266
267 status = fpga_boot(dst, len);
268 if (status != 0) {
269 printf("\nFPGA: Booting failed ");
270 switch (status) {
271 case ERROR_FPGA_PRG_INIT_LOW:
272 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
273 break;
274 case ERROR_FPGA_PRG_INIT_HIGH:
275 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
276 break;
277 case ERROR_FPGA_PRG_DONE:
278 printf("(Timeout: DONE not high after programming FPGA)\n ");
279 break;
280 }
281
282 /* display infos on fpgaimage */
283 index = 15;
284 for (i=0; i<4; i++) {
285 len = dst[index];
286 printf("FPGA: %s\n", &(dst[index+1]));
287 index += len+3;
288 }
289 putc ('\n');
290 /* delayed reboot */
291 for (i=20; i>0; i--) {
292 printf("Rebooting in %2d seconds \r",i);
293 for (index=0;index<1000;index++)
294 udelay(1000);
295 }
296 putc ('\n');
297 do_reset(NULL, 0, 0, NULL);
298 }
299
300 /* restore gpio/cs settings */
301 mtdcr(cntrl0, cntrl0Reg);
302
303 puts("FPGA: ");
304
305 /* display infos on fpgaimage */
306 index = 15;
307 for (i=0; i<4; i++) {
308 len = dst[index];
309 printf("%s ", &(dst[index+1]));
310 index += len+3;
311 }
312 putc ('\n');
313
314 free(dst);
stroese6f4474e2003-03-20 15:31:19 +0000315
316 /*
317 * Reset FPGA via FPGA_DATA pin
318 */
319 SET_FPGA(FPGA_PRG | FPGA_CLK);
320 udelay(1000); /* wait 1ms */
321 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
322 udelay(1000); /* wait 1ms */
323
324 if (cpci405_version() == 3) {
325 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
326 volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
327
328 /*
329 * Enable outputs in fpga on version 3 board
330 */
331 *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
332
333 /*
334 * Set outputs to 0
335 */
336 *leds = 0x00;
337
338 /*
339 * Reset external DUART
340 */
341 *fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
342 udelay(100);
343 *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
344 }
wdenkc6097192002-11-03 00:24:07 +0000345 }
346 else {
stroese6f4474e2003-03-20 15:31:19 +0000347 puts("\n*** U-Boot Version does not match Board Version!\n");
348 puts("*** CPCI-405 Version 1.x detected!\n");
349 puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
wdenkc6097192002-11-03 00:24:07 +0000350 }
351
352#else /* CONFIG_CPCI405_VER2 */
353
354 /*
355 * Generate last byte of ip-addr from code-plug @ 0xf0000400
356 */
357 if (ctermm2()) {
358 char str[32];
359 unsigned char ipbyte = *(unsigned char *)0xf0000400;
360
361 /*
362 * Only overwrite ip-addr with allowed values
363 */
364 if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
365 bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
366 sprintf(str, "%ld.%ld.%ld.%ld",
367 (bd->bi_ip_addr & 0xff000000) >> 24,
368 (bd->bi_ip_addr & 0x00ff0000) >> 16,
369 (bd->bi_ip_addr & 0x0000ff00) >> 8,
370 (bd->bi_ip_addr & 0x000000ff));
371 setenv("ipaddr", str);
372 }
373 }
374
stroese6f4474e2003-03-20 15:31:19 +0000375 if (cpci405_version() >= 2) {
376 puts("\n*** U-Boot Version does not match Board Version!\n");
377 puts("*** CPCI-405 Board Version 2.x detected!\n");
378 puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
wdenkc6097192002-11-03 00:24:07 +0000379 }
380
381#endif /* CONFIG_CPCI405_VER2 */
382
383 /*
stroeseafcc4a72003-04-04 16:52:57 +0000384 * Select cts (and not dsr) on uart1
385 */
386 cntrl0Reg = mfdcr(cntrl0);
387 mtdcr(cntrl0, cntrl0Reg | 0x00001000);
388
389 /*
wdenkc6097192002-11-03 00:24:07 +0000390 * Write ethernet addr in NVRAM for VxWorks
391 */
392 tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;
393 memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 );
394 return (0);
395}
396
397
398/*
399 * Check Board Identity:
400 */
401
402int checkboard (void)
403{
404#ifndef CONFIG_CPCI405_VER2
405 int index;
406 int len;
407#endif
408 unsigned char str[64];
409 int i = getenv_r ("serial#", str, sizeof(str));
stroese6f4474e2003-03-20 15:31:19 +0000410 unsigned short ver;
wdenkc6097192002-11-03 00:24:07 +0000411
412 puts ("Board: ");
413
414 if (i == -1) {
415 puts ("### No HW ID - assuming CPCI405");
416 } else {
417 puts(str);
418 }
419
stroese6f4474e2003-03-20 15:31:19 +0000420 ver = cpci405_version();
421 printf(" (Ver %d.x, ", ver);
wdenkc6097192002-11-03 00:24:07 +0000422
stroese6f4474e2003-03-20 15:31:19 +0000423#if 0 /* test-only */
424 if (ver >= 2) {
425 volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
426
427 if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
428 puts ("FLASH Bank B, ");
429 } else {
430 puts ("FLASH Bank A, ");
431 }
432 }
wdenkc6097192002-11-03 00:24:07 +0000433#endif
434
435 if (ctermm2()) {
stroese1b554402003-09-12 08:44:46 +0000436 unsigned char str[4];
437
438 /*
439 * Read board-id and save in env-variable
440 */
441 sprintf(str, "%d", *(unsigned char *)0xf0000400);
442 setenv("boardid", str);
443 printf("CTERM-M2 - Id=%s)", str);
wdenkc6097192002-11-03 00:24:07 +0000444 } else {
445 if (cpci405_host()) {
446 puts ("PCI Host Version)");
447 } else {
448 puts ("PCI Adapter Version)");
449 }
450 }
451
452#ifndef CONFIG_CPCI405_VER2
453 puts ("\nFPGA: ");
454
455 /* display infos on fpgaimage */
456 index = 15;
457 for (i=0; i<4; i++) {
458 len = fpgadata[index];
459 printf("%s ", &(fpgadata[index+1]));
460 index += len+3;
461 }
462#endif
463
464 putc ('\n');
465
466 return 0;
467}
468
469/* ------------------------------------------------------------------------- */
470
471long int initdram (int board_type)
472{
473 unsigned long val;
474
475 mtdcr(memcfga, mem_mb0cf);
476 val = mfdcr(memcfgd);
477
478#if 0
479 printf("\nmb0cf=%x\n", val); /* test-only */
480 printf("strap=%x\n", mfdcr(strap)); /* test-only */
481#endif
482
483 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
484}
485
486/* ------------------------------------------------------------------------- */
487
488int testdram (void)
489{
490 /* TODO: XXX XXX XXX */
491 printf ("test: 16 MB - ok\n");
492
493 return (0);
494}
495
496/* ------------------------------------------------------------------------- */
497
498#ifdef CONFIG_CPCI405_VER2
499#ifdef CONFIG_IDE_RESET
500
501void ide_set_reset(int on)
502{
503 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
504
505 /*
506 * Assert or deassert CompactFlash Reset Pin
507 */
508 if (on) { /* assert RESET */
509 *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
510 } else { /* release RESET */
511 *fpga_mode |= CFG_FPGA_MODE_CF_RESET;
512 }
513}
514
515#endif /* CONFIG_IDE_RESET */
516#endif /* CONFIG_CPCI405_VER2 */
517
stroesed4629c82003-05-23 11:30:39 +0000518
stroese1b554402003-09-12 08:44:46 +0000519#ifdef CONFIG_CPCI405AB
520
521#define ONE_WIRE_CLEAR (*(volatile unsigned short *)0xf0400000 |= 0x0100)
522#define ONE_WIRE_SET (*(volatile unsigned short *)0xf0400000 &= ~0x0100)
523#define ONE_WIRE_GET (*(volatile unsigned short *)0xf0400002 & 0x1000)
524
525/*
526 * Generate a 1-wire reset, return 1 if no presence detect was found,
527 * return 0 otherwise.
528 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
529 */
530int OWTouchReset(void)
stroesed4629c82003-05-23 11:30:39 +0000531{
stroese1b554402003-09-12 08:44:46 +0000532 int result;
stroesed4629c82003-05-23 11:30:39 +0000533
stroese1b554402003-09-12 08:44:46 +0000534 ONE_WIRE_CLEAR;
535 udelay(480);
536 ONE_WIRE_SET;
537 udelay(70);
stroesed4629c82003-05-23 11:30:39 +0000538
stroese1b554402003-09-12 08:44:46 +0000539 result = ONE_WIRE_GET;
540
541 udelay(410);
542 return result;
stroesed4629c82003-05-23 11:30:39 +0000543}
544
545
stroese1b554402003-09-12 08:44:46 +0000546/*
547 * Send 1 a 1-wire write bit.
548 * Provide 10us recovery time.
549 */
550void OWWriteBit(int bit)
stroesed4629c82003-05-23 11:30:39 +0000551{
stroese1b554402003-09-12 08:44:46 +0000552 if (bit) {
553 /*
554 * write '1' bit
555 */
556 ONE_WIRE_CLEAR;
557 udelay(6);
558 ONE_WIRE_SET;
559 udelay(64);
560 } else {
561 /*
562 * write '0' bit
563 */
564 ONE_WIRE_CLEAR;
565 udelay(60);
566 ONE_WIRE_SET;
567 udelay(10);
stroesed4629c82003-05-23 11:30:39 +0000568 }
stroesed4629c82003-05-23 11:30:39 +0000569}
570
stroese1b554402003-09-12 08:44:46 +0000571
572/*
573 * Read a bit from the 1-wire bus and return it.
574 * Provide 10us recovery time.
575 */
576int OWReadBit(void)
577{
578 int result;
579
580 ONE_WIRE_CLEAR;
581 udelay(6);
582 ONE_WIRE_SET;
583 udelay(9);
584
585 result = ONE_WIRE_GET;
586
587 udelay(55);
588 return result;
589}
590
591
592void OWWriteByte(int data)
593{
594 int loop;
595
596 for (loop=0; loop<8; loop++) {
597 OWWriteBit(data & 0x01);
598 data >>= 1;
599 }
600}
601
602
603int OWReadByte(void)
604{
605 int loop, result = 0;
606
607 for (loop=0; loop<8; loop++) {
608 result >>= 1;
609 if (OWReadBit()) {
610 result |= 0x80;
611 }
612 }
613
614 return result;
615}
616
617
618int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
619{
620 volatile unsigned short val;
621 int result;
622 int i;
623 unsigned char ow_id[6];
624 unsigned char str[32];
625 unsigned char ow_crc;
626
627 /*
628 * Clear 1-wire bit (open drain with pull-up)
629 */
630 val = *(volatile unsigned short *)0xf0400000;
631 val &= ~0x1000; /* clear 1-wire bit */
632 *(volatile unsigned short *)0xf0400000 = val;
633
634 result = OWTouchReset();
635 if (result != 0) {
636 puts("No 1-wire device detected!\n");
637 }
638
639 OWWriteByte(0x33); /* send read rom command */
640 OWReadByte(); /* skip family code ( == 0x01) */
641 for (i=0; i<6; i++) {
642 ow_id[i] = OWReadByte();
643 }
644 ow_crc = OWReadByte(); /* read crc */
645
646 sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
647 printf("Setting environment variable 'ow_id' to %s\n", str);
648 setenv("ow_id", str);
649
650 return 0;
651}
652U_BOOT_CMD(
653 onewire, 1, 1, do_onewire,
654 "onewire - Read 1-write ID\n",
655 NULL
656 );
657
658#endif /* CONFIG_CPCI405AB */