blob: 021da50aa83144f37dc27f3850d82334f223b3e2 [file] [log] [blame]
Joe Hammanc646bba2007-08-09 15:11:03 -05001/*
2 * Copyright 2007 Wind River Systems <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman <joe.hamman@embeddedspecialties.com>
5 *
6 * Copyright 2006 Freescale Semiconductor.
7 *
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
Joe Hammanc646bba2007-08-09 15:11:03 -050011 */
12
13/*
14 * SBC8641D board configuration file
15 *
16 * Make sure you change the MAC address and other network params first,
Joe Hershberger92ac5202015-05-04 14:55:14 -050017 * search for CONFIG_SERVERIP, etc in this file.
Joe Hammanc646bba2007-08-09 15:11:03 -050018 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/* High Level Configuration Options */
Joe Hammanc646bba2007-08-09 15:11:03 -050024#define CONFIG_MPC8641 1 /* MPC8641 specific */
25#define CONFIG_SBC8641D 1 /* SBC8641D board specific */
Kumar Gala7649a592009-03-31 23:02:38 -050026#define CONFIG_MP 1 /* support multiple processors */
Joe Hammanc646bba2007-08-09 15:11:03 -050027#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
28
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029#define CONFIG_SYS_TEXT_BASE 0xfff00000
30
Joe Hammanc646bba2007-08-09 15:11:03 -050031#ifdef RUN_DIAG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_DIAG_ADDR 0xff800000
Joe Hammanc646bba2007-08-09 15:11:03 -050033#endif
34
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
Joe Hammanc646bba2007-08-09 15:11:03 -050036
Becky Bruce1266df82008-11-03 15:44:01 -060037/*
38 * virtual address to be used for temporary mappings. There
39 * should be 128k free at this VA.
40 */
41#define CONFIG_SYS_SCRATCH_VA 0xe8000000
42
Kumar Gala7cee1df2011-01-04 17:48:51 -060043#define CONFIG_SYS_SRIO
44#define CONFIG_SRIO1 /* SRIO port 1 */
45
Joe Hammancca34962007-08-11 06:54:58 -050046#define CONFIG_PCI 1 /* Enable PCIE */
Kumar Gala46f3e382010-07-09 00:02:34 -050047#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
48#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
Joe Hammancca34962007-08-11 06:54:58 -050049#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000050#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Becky Bruce713d8182008-01-23 16:31:03 -060051#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hammanc646bba2007-08-09 15:11:03 -050052
Wolfgang Denk53677ef2008-05-20 16:00:29 +020053#define CONFIG_TSEC_ENET /* tsec ethernet support */
Joe Hammanc646bba2007-08-09 15:11:03 -050054#define CONFIG_ENV_OVERWRITE
55
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050056#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce23f935c2008-08-04 14:01:16 -050057#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
58
Joe Hammanc646bba2007-08-09 15:11:03 -050059#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
Wolfgang Denk53677ef2008-05-20 16:00:29 +020060#undef CONFIG_DDR_ECC /* only for ECC DDR module */
Joe Hammanc646bba2007-08-09 15:11:03 -050061#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
62#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
63#define CONFIG_NUM_DDR_CONTROLLERS 2
64#define CACHE_LINE_INTERLEAVING 0x20000000
65#define PAGE_INTERLEAVING 0x21000000
66#define BANK_INTERLEAVING 0x22000000
67#define SUPER_BANK_INTERLEAVING 0x23000000
68
69
70#define CONFIG_ALTIVEC 1
71
72/*
73 * L2CR setup -- make sure this is right for your board!
74 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_L2
Joe Hammanc646bba2007-08-09 15:11:03 -050076#define L2_INIT 0
77#define L2_ENABLE (L2CR_L2E)
78
79#ifndef CONFIG_SYS_CLK_FREQ
80#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
81#endif
82
83#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
84
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
86#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
87#define CONFIG_SYS_MEMTEST_END 0x00400000
Joe Hammanc646bba2007-08-09 15:11:03 -050088
89/*
90 * Base addresses -- Note these are effective addresses where the
91 * actual resources get mapped (not physical addresses)
92 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
94#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
95#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Joe Hammanc646bba2007-08-09 15:11:03 -050096
Jon Loeligerf6987382008-11-20 14:02:56 -060097#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
98#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
Kumar Galaad19e7a2009-08-05 07:59:35 -050099#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
Jon Loeligerf6987382008-11-20 14:02:56 -0600100
Joe Hammanc646bba2007-08-09 15:11:03 -0500101/*
102 * DDR Setup
103 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
105#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
106#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
107#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
Becky Bruce1266df82008-11-03 15:44:01 -0600108#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Joe Hammanc646bba2007-08-09 15:11:03 -0500109#define CONFIG_VERY_BIG_RAM
110
Kumar Gala9bd4e592008-08-26 15:01:37 -0500111#define CONFIG_NUM_DDR_CONTROLLERS 2
112#define CONFIG_DIMM_SLOTS_PER_CTLR 2
113#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
114
Joe Hammanc646bba2007-08-09 15:11:03 -0500115#if defined(CONFIG_SPD_EEPROM)
116 /*
117 * Determine DDR configuration from I2C interface.
118 */
119 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
120 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
121 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
122 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
123
124#else
125 /*
126 * Manually set up DDR1 & DDR2 parameters
127 */
128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
Joe Hammanc646bba2007-08-09 15:11:03 -0500130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
132 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
133 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
134 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
135 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
136 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
137 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
138 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
139 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
140 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
141 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
142 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
143 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
144 #define CONFIG_SYS_DDR_CFG_2 0x24401000
145 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
146 #define CONFIG_SYS_DDR_MODE_2 0x00000000
147 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
148 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
149 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
150 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
151 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
Joe Hammanc646bba2007-08-09 15:11:03 -0500152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
154 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
155 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
156 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
157 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
158 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
159 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
160 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
161 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
162 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
163 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
164 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
165 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
166 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
167 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
168 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
169 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
170 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
171 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
172 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
173 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
Joe Hammanc646bba2007-08-09 15:11:03 -0500174
175
176#endif
177
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200178/* #define CONFIG_ID_EEPROM 1
Joe Hammanc646bba2007-08-09 15:11:03 -0500179#define ID_EEPROM_ADDR 0x57 */
180
181/*
182 * The SBC8641D contains 16MB flash space at ff000000.
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
Joe Hammanc646bba2007-08-09 15:11:03 -0500185
186/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
188#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
Joe Hammanc646bba2007-08-09 15:11:03 -0500189
190/* 64KB EEPROM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
192#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
Joe Hammanc646bba2007-08-09 15:11:03 -0500193
194/* EPLD - User switches, board id, LEDs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
196#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
Joe Hammanc646bba2007-08-09 15:11:03 -0500197
198/* Local bus SDRAM 128MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
200#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
201#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
202#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
Joe Hammanc646bba2007-08-09 15:11:03 -0500203
204/* Disk on Chip (DOC) 128MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
206#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
Joe Hammanc646bba2007-08-09 15:11:03 -0500207
208/* LCD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
210#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
Joe Hammanc646bba2007-08-09 15:11:03 -0500211
212/* Control logic & misc peripherals */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
214#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
Joe Hammanc646bba2007-08-09 15:11:03 -0500215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
217#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
Joe Hammanc646bba2007-08-09 15:11:03 -0500218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#undef CONFIG_SYS_FLASH_CHECKSUM
220#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
221#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200222#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600223#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Joe Hammanc646bba2007-08-09 15:11:03 -0500224
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200225#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_CFI
227#define CONFIG_SYS_WRITE_SWAPPED_DATA
228#define CONFIG_SYS_FLASH_EMPTY_INFO
229#define CONFIG_SYS_FLASH_PROTECTION
Joe Hammanc646bba2007-08-09 15:11:03 -0500230
231#undef CONFIG_CLOCKS_IN_MHZ
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_INIT_RAM_LOCK 1
234#ifndef CONFIG_SYS_INIT_RAM_LOCK
235#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
Joe Hammanc646bba2007-08-09 15:11:03 -0500236#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
Joe Hammanc646bba2007-08-09 15:11:03 -0500238#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200239#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Joe Hammanc646bba2007-08-09 15:11:03 -0500240
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200241#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Joe Hammanc646bba2007-08-09 15:11:03 -0500243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
245#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Joe Hammanc646bba2007-08-09 15:11:03 -0500246
247/* Serial Port */
248#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_NS16550
250#define CONFIG_SYS_NS16550_SERIAL
251#define CONFIG_SYS_NS16550_REG_SIZE 1
252#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Joe Hammanc646bba2007-08-09 15:11:03 -0500253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hammanc646bba2007-08-09 15:11:03 -0500255 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
258#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Joe Hammanc646bba2007-08-09 15:11:03 -0500259
260/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_HUSH_PARSER
262#ifdef CONFIG_SYS_HUSH_PARSER
Joe Hammanc646bba2007-08-09 15:11:03 -0500263#endif
264
265/*
266 * Pass open firmware flat tree to kernel
267 */
Jon Loeliger13f54332008-02-18 14:01:56 -0600268#define CONFIG_OF_LIBFDT 1
269#define CONFIG_OF_BOARD_SETUP 1
270#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Joe Hammanc646bba2007-08-09 15:11:03 -0500271
Joe Hammanc646bba2007-08-09 15:11:03 -0500272/*
273 * I2C
274 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200275#define CONFIG_SYS_I2C
276#define CONFIG_SYS_I2C_FSL
277#define CONFIG_SYS_FSL_I2C_SPEED 400000
278#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
279#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
280#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Joe Hammanc646bba2007-08-09 15:11:03 -0500281
282/*
283 * RapidIO MMU
284 */
Kumar Gala7cee1df2011-01-04 17:48:51 -0600285#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
286#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
287#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
Joe Hammanc646bba2007-08-09 15:11:03 -0500288
289/*
290 * General PCI
291 * Addresses are mapped 1-1.
292 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500293#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
294#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
295#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
296#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
297#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
298#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
299#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
300#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
Joe Hammanc646bba2007-08-09 15:11:03 -0500301
Kumar Gala46f3e382010-07-09 00:02:34 -0500302#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
303#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
304#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
305#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
306#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
307#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
308#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
309#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
Joe Hammanc646bba2007-08-09 15:11:03 -0500310
311#if defined(CONFIG_PCI)
312
313#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
Joe Hammanc646bba2007-08-09 15:11:03 -0500316
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200317#define CONFIG_PCI_PNP /* do pci plug-and-play */
Joe Hammanc646bba2007-08-09 15:11:03 -0500318
319#undef CONFIG_EEPRO100
320#undef CONFIG_TULIP
321
322#if !defined(CONFIG_PCI_PNP)
323 #define PCI_ENET0_IOADDR 0xe0000000
324 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200325 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Joe Hammanc646bba2007-08-09 15:11:03 -0500326#endif
327
328#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
329
330#define CONFIG_DOS_PARTITION
331#undef CONFIG_SCSI_AHCI
332
333#ifdef CONFIG_SCSI_AHCI
334#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
336#define CONFIG_SYS_SCSI_MAX_LUN 1
337#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
338#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Joe Hammanc646bba2007-08-09 15:11:03 -0500339#endif
340
341#endif /* CONFIG_PCI */
342
343#if defined(CONFIG_TSEC_ENET)
344
Joe Hammanc646bba2007-08-09 15:11:03 -0500345/* #define CONFIG_MII 1 */ /* MII PHY management */
346
347#define CONFIG_TSEC1 1
348#define CONFIG_TSEC1_NAME "eTSEC1"
349#define CONFIG_TSEC2 1
350#define CONFIG_TSEC2_NAME "eTSEC2"
351#define CONFIG_TSEC3 1
352#define CONFIG_TSEC3_NAME "eTSEC3"
353#define CONFIG_TSEC4 1
354#define CONFIG_TSEC4_NAME "eTSEC4"
355
356#define TSEC1_PHY_ADDR 0x1F
357#define TSEC2_PHY_ADDR 0x00
358#define TSEC3_PHY_ADDR 0x01
359#define TSEC4_PHY_ADDR 0x02
360#define TSEC1_PHYIDX 0
361#define TSEC2_PHYIDX 0
362#define TSEC3_PHYIDX 0
363#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500364#define TSEC1_FLAGS TSEC_GIGABIT
365#define TSEC2_FLAGS TSEC_GIGABIT
366#define TSEC3_FLAGS TSEC_GIGABIT
367#define TSEC4_FLAGS TSEC_GIGABIT
Joe Hammanc646bba2007-08-09 15:11:03 -0500368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
Joe Hammanc646bba2007-08-09 15:11:03 -0500370
371#define CONFIG_ETHPRIME "eTSEC1"
372
373#endif /* CONFIG_TSEC_ENET */
374
375/*
376 * BAT0 2G Cacheable, non-guarded
377 * 0x0000_0000 2G DDR
378 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
380#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
381#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
382#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
Joe Hammanc646bba2007-08-09 15:11:03 -0500383
384/*
385 * BAT1 1G Cache-inhibited, guarded
386 * 0x8000_0000 512M PCI-Express 1 Memory
387 * 0xa000_0000 512M PCI-Express 2 Memory
388 * Changed it for operating from 0xd0000000
389 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500390#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500391 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500392#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
393#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Joe Hammanc646bba2007-08-09 15:11:03 -0500395
396/*
397 * BAT2 512M Cache-inhibited, guarded
398 * 0xc000_0000 512M RapidIO Memory
399 */
Kumar Gala7cee1df2011-01-04 17:48:51 -0600400#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500401 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Kumar Gala7cee1df2011-01-04 17:48:51 -0600402#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
403#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Joe Hammanc646bba2007-08-09 15:11:03 -0500405
406/*
407 * BAT3 4M Cache-inhibited, guarded
408 * 0xf800_0000 4M CCSR
409 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500411 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
413#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
414#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
Joe Hammanc646bba2007-08-09 15:11:03 -0500415
Jon Loeligerf6987382008-11-20 14:02:56 -0600416#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
417#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
418 | BATL_PP_RW | BATL_CACHEINHIBIT \
419 | BATL_GUARDEDSTORAGE)
420#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
421 | BATU_BL_1M | BATU_VS | BATU_VP)
422#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
423 | BATL_PP_RW | BATL_CACHEINHIBIT)
424#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
425#endif
426
Joe Hammanc646bba2007-08-09 15:11:03 -0500427/*
428 * BAT4 32M Cache-inhibited, guarded
429 * 0xe200_0000 16M PCI-Express 1 I/O
430 * 0xe300_0000 16M PCI-Express 2 I/0
431 * Note that this is at 0xe0000000
432 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500433#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500434 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500435#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
436#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Joe Hammanc646bba2007-08-09 15:11:03 -0500438
439/*
440 * BAT5 128K Cacheable, non-guarded
441 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
442 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
444#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
445#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
446#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Joe Hammanc646bba2007-08-09 15:11:03 -0500447
448/*
449 * BAT6 32M Cache-inhibited, guarded
450 * 0xfe00_0000 32M FLASH
451 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
Joe Hammanc646bba2007-08-09 15:11:03 -0500453 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
455#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
456#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Joe Hammanc646bba2007-08-09 15:11:03 -0500457
Becky Brucebf9a8c32008-11-05 14:55:35 -0600458/* Map the last 1M of flash where we're running from reset */
459#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
460 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200461#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600462#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
463 | BATL_MEMCOHERENCE)
464#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
465
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_DBAT7L 0x00000000
467#define CONFIG_SYS_DBAT7U 0x00000000
468#define CONFIG_SYS_IBAT7L 0x00000000
469#define CONFIG_SYS_IBAT7U 0x00000000
Joe Hammanc646bba2007-08-09 15:11:03 -0500470
471/*
472 * Environment
473 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200474#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200476#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
477#define CONFIG_ENV_SIZE 0x2000
Joe Hammanc646bba2007-08-09 15:11:03 -0500478
479#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Joe Hammanc646bba2007-08-09 15:11:03 -0500481
482#include <config_cmd_default.h>
483 #define CONFIG_CMD_PING
484 #define CONFIG_CMD_I2C
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600485 #define CONFIG_CMD_REGINFO
Joe Hammanc646bba2007-08-09 15:11:03 -0500486
487#if defined(CONFIG_PCI)
488 #define CONFIG_CMD_PCI
489#endif
490
491#undef CONFIG_WATCHDOG /* watchdog disabled */
492
493/*
494 * Miscellaneous configurable options
495 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_LONGHELP /* undef to save memory */
497#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Joe Hammanc646bba2007-08-09 15:11:03 -0500498
Jon Loeliger30b52df2007-08-15 11:55:35 -0500499#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Joe Hammanc646bba2007-08-09 15:11:03 -0500501#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200502 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Joe Hammanc646bba2007-08-09 15:11:03 -0500503#endif
504
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
506#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
507#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Joe Hammanc646bba2007-08-09 15:11:03 -0500508
509/*
510 * For booting Linux, the board info and command line data
511 * have to be in the first 8 MB of memory, since this is
512 * the maximum mapped by the Linux kernel during initialization.
513 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Joe Hammanc646bba2007-08-09 15:11:03 -0500515
516/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517#define CONFIG_SYS_DCACHE_SIZE 32768
518#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger30b52df2007-08-15 11:55:35 -0500519#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
Joe Hammanc646bba2007-08-09 15:11:03 -0500521#endif
522
Jon Loeliger30b52df2007-08-15 11:55:35 -0500523#if defined(CONFIG_CMD_KGDB)
Joe Hammanc646bba2007-08-09 15:11:03 -0500524#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Joe Hammanc646bba2007-08-09 15:11:03 -0500525#endif
526
527/*
528 * Environment Configuration
529 */
530
Andy Fleming10327dc2007-08-16 16:35:02 -0500531#define CONFIG_HAS_ETH0 1
Joe Hammanc646bba2007-08-09 15:11:03 -0500532#define CONFIG_HAS_ETH1 1
533#define CONFIG_HAS_ETH2 1
534#define CONFIG_HAS_ETH3 1
535
536#define CONFIG_IPADDR 192.168.0.50
537
538#define CONFIG_HOSTNAME sbc8641d
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000539#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000540#define CONFIG_BOOTFILE "uImage"
Joe Hammanc646bba2007-08-09 15:11:03 -0500541
542#define CONFIG_SERVERIP 192.168.0.2
543#define CONFIG_GATEWAYIP 192.168.0.1
544#define CONFIG_NETMASK 255.255.255.0
545
546/* default location for tftp and bootm */
547#define CONFIG_LOADADDR 1000000
548
549#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
550#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
551
552#define CONFIG_BAUDRATE 115200
553
554#define CONFIG_EXTRA_ENV_SETTINGS \
555 "netdev=eth0\0" \
556 "consoledev=ttyS0\0" \
557 "ramdiskaddr=2000000\0" \
558 "ramdiskfile=uRamdisk\0" \
559 "dtbaddr=400000\0" \
560 "dtbfile=sbc8641d.dtb\0" \
561 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
562 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
563 "maxcpus=1"
564
565#define CONFIG_NFSBOOTCOMMAND \
566 "setenv bootargs root=/dev/nfs rw " \
567 "nfsroot=$serverip:$rootpath " \
568 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
569 "console=$consoledev,$baudrate $othbootargs;" \
570 "tftp $loadaddr $bootfile;" \
571 "tftp $dtbaddr $dtbfile;" \
572 "bootm $loadaddr - $dtbaddr"
573
574#define CONFIG_RAMBOOTCOMMAND \
575 "setenv bootargs root=/dev/ram rw " \
576 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
577 "console=$consoledev,$baudrate $othbootargs;" \
578 "tftp $ramdiskaddr $ramdiskfile;" \
579 "tftp $loadaddr $bootfile;" \
580 "tftp $dtbaddr $dtbfile;" \
581 "bootm $loadaddr $ramdiskaddr $dtbaddr"
582
583#define CONFIG_FLASHBOOTCOMMAND \
584 "setenv bootargs root=/dev/ram rw " \
585 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
586 "console=$consoledev,$baudrate $othbootargs;" \
587 "bootm ffd00000 ffb00000 ffa00000"
588
589#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
590
591#endif /* __CONFIG_H */