| Niklaus Giger | 157cda4 | 2007-07-27 11:31:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * See file CREDITS for list of people who contributed to this |
| 4 | * project. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #include <ppc_asm.tmpl> |
| 23 | #include <config.h> |
| 24 | #include <asm/mmu.h> |
| 25 | |
| 26 | /************************************************************************** |
| 27 | * TLB TABLE |
| 28 | * |
| 29 | * This table is used by the cpu boot code to setup the initial tlb |
| 30 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 31 | * this table lets each board set things up however they like. |
| 32 | * |
| 33 | * Pointer to the table is returned in r1 |
| 34 | * |
| 35 | *************************************************************************/ |
| 36 | .section .bootpg,"ax" |
| 37 | .globl tlbtab |
| 38 | |
| 39 | tlbtab: |
| 40 | tlbtab_start |
| 41 | |
| 42 | /* vxWorks needs this entry for the Machine Check interrupt, */ |
| 43 | /* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ |
| 44 | |
| 45 | /* |
| 46 | * BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the |
| 47 | * speed up boot process. It is patched after relocation to enable SA_I |
| 48 | */ |
| 49 | tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) |
| 50 | |
| 51 | /* TLB-entry for PCI Memory */ |
| 52 | tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) |
| 53 | tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) |
| 54 | tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) |
| 55 | tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) |
| 56 | |
| 57 | /* TLB-entry for EBC (CFG_CPLD) */ |
| Stefan Roese | 35d22f9 | 2007-08-10 10:42:25 +0200 | [diff] [blame] | 58 | /* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ |
| Niklaus Giger | 157cda4 | 2007-07-27 11:31:22 +0200 | [diff] [blame] | 59 | /* CAN */ |
| 60 | tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
| 61 | /* IMC + CPLD */ |
| 62 | tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
| 63 | tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
| 64 | /* IMC-Fast */ |
| 65 | tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
| 66 | tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
| 67 | |
| 68 | /* TLB-entry for Internal Registers & OCM */ |
| 69 | tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) |
| 70 | |
| 71 | /*TLB-entry PCI registers*/ |
| 72 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
| 73 | |
| 74 | /* TLB-entry for peripherals */ |
| 75 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) |
| 76 | |
| 77 | /* TLB for SDRAM will be added by initdram (sdram.c) */ |
| 78 | |
| 79 | tlbtab_end |