blob: 00facf492e0d4341baad41b315dfec905bea946f [file] [log] [blame]
Trevor Woerner18138ab2020-05-06 08:02:41 -04001if ARCH_TEGRA
Masahiro Yamadaddd960e2014-08-31 07:10:56 +09002
Simon Glass53b5bf32016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glass77d2f7f2016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glasscc4288e2016-09-12 23:18:43 -06009config SPL_LIBGENERIC_SUPPORT
10 default y
11
Simon Glasse00f76c2016-09-12 23:18:56 -060012config SPL_SERIAL_SUPPORT
13 default y
14
Thierry Redingb64e0b92019-04-15 11:32:18 +020015config TEGRA_CLKRST
16 bool
17
Thierry Reding9e578192019-04-15 11:32:19 +020018config TEGRA_GP_PADCTRL
19 bool
20
Stephen Warren49626ea2016-07-18 12:17:11 -060021config TEGRA_IVC
22 bool "Tegra IVC protocol"
23 help
24 IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
25 (Inter Processor Communication) framework. Within the context of
26 U-Boot, it is typically used for communication between the main CPU
27 and various auxiliary processors.
28
Thierry Reding1a869c72019-04-15 11:32:20 +020029config TEGRA_MC
30 bool
31
Thierry Reding07ea02b2019-04-15 11:32:21 +020032config TEGRA_PINCTRL
33 bool
34
Thierry Redinge19143b2019-04-15 11:32:22 +020035config TEGRA_PMC
36 bool
37
Thierry Redingf9ec2ec2019-04-15 11:32:25 +020038config TEGRA_PMC_SECURE
39 bool
40 depends on TEGRA_PMC
41
Stephen Warren15bcc622015-11-23 10:32:01 -070042config TEGRA_COMMON
43 bool "Tegra common options"
Michal Simek5ed063d2018-07-23 15:55:13 +020044 select BINMAN
45 select BOARD_EARLY_INIT_F
Stephen Warren140a9ea2016-09-13 10:46:00 -060046 select CLK
Tom Warren56079ec2015-07-17 08:12:51 -070047 select DM
Simon Glass96350f72015-11-29 13:18:01 -070048 select DM_ETH
Tom Warren56079ec2015-07-17 08:12:51 -070049 select DM_GPIO
Stephen Warren15bcc622015-11-23 10:32:01 -070050 select DM_I2C
Simon Glassf77f5e92015-10-18 21:17:16 -060051 select DM_KEYBOARD
Tom Warren6a474db2016-09-13 10:45:48 -060052 select DM_MMC
Simon Glass91c08af2016-01-30 16:38:01 -070053 select DM_PWM
Stephen Warren140a9ea2016-09-13 10:46:00 -060054 select DM_RESET
Stephen Warren15bcc622015-11-23 10:32:01 -070055 select DM_SERIAL
56 select DM_SPI
57 select DM_SPI_FLASH
Stephen Warren140a9ea2016-09-13 10:46:00 -060058 select MISC
Stephen Warren15bcc622015-11-23 10:32:01 -070059 select OF_CONTROL
Michal Simek5ed063d2018-07-23 15:55:13 +020060 select SPI
Simon Glassd6ef8a62016-02-16 18:09:19 -070061 select VIDCONSOLE_AS_LCD if DM_VIDEO
Michal Simek08a00cb2018-07-23 15:55:14 +020062 imply CMD_DM
Daniel Thompson221a9492017-05-19 17:26:58 +010063 imply CRC32_VERIFY
Stephen Warren15bcc622015-11-23 10:32:01 -070064
Stephen Warren140a9ea2016-09-13 10:46:00 -060065config TEGRA_NO_BPMP
66 bool "Tegra common options for SoCs without BPMP"
67 select TEGRA_CAR
68 select TEGRA_CAR_CLOCK
69 select TEGRA_CAR_RESET
70
Stephen Warren15bcc622015-11-23 10:32:01 -070071config TEGRA_ARMV7_COMMON
72 bool "Tegra 32-bit common options"
Lokesh Vutlaacf15002018-04-26 18:21:26 +053073 select CPU_V7A
Stephen Warren15bcc622015-11-23 10:32:01 -070074 select SPL
Ley Foon Tan0680f1b2017-05-03 17:13:32 +080075 select SPL_BOARD_INIT if SPL
Stephen Warren15bcc622015-11-23 10:32:01 -070076 select SUPPORT_SPL
Thierry Redingb64e0b92019-04-15 11:32:18 +020077 select TEGRA_CLKRST
Stephen Warren15bcc622015-11-23 10:32:01 -070078 select TEGRA_COMMON
Stephen Warren601800b2016-05-12 12:07:41 -060079 select TEGRA_GPIO
Thierry Reding9e578192019-04-15 11:32:19 +020080 select TEGRA_GP_PADCTRL
Thierry Reding1a869c72019-04-15 11:32:20 +020081 select TEGRA_MC
Stephen Warren140a9ea2016-09-13 10:46:00 -060082 select TEGRA_NO_BPMP
Thierry Reding07ea02b2019-04-15 11:32:21 +020083 select TEGRA_PINCTRL
Thierry Redinge19143b2019-04-15 11:32:22 +020084 select TEGRA_PMC
Stephen Warren15bcc622015-11-23 10:32:01 -070085
86config TEGRA_ARMV8_COMMON
87 bool "Tegra 64-bit common options"
88 select ARM64
Masahiro Yamada382de4a2019-06-26 13:51:46 +090089 select INIT_SP_RELATIVE
Stephen Warrenddecaaf2018-01-03 14:31:52 -070090 select LINUX_KERNEL_IMAGE_HEADER
Thierry Reding74a50ac2019-04-15 11:32:32 +020091 select POSITION_INDEPENDENT
Stephen Warren15bcc622015-11-23 10:32:01 -070092 select TEGRA_COMMON
Tom Warren56079ec2015-07-17 08:12:51 -070093
Stephen Warrenddecaaf2018-01-03 14:31:52 -070094if TEGRA_ARMV8_COMMON
95config LNX_KRNL_IMG_TEXT_OFFSET_BASE
96 default 0x80000000
97endif
98
Masahiro Yamadaddd960e2014-08-31 07:10:56 +090099choice
100 prompt "Tegra SoC select"
Joe Hershbergera26cd042015-05-12 14:46:23 -0500101 optional
Masahiro Yamadaddd960e2014-08-31 07:10:56 +0900102
103config TEGRA20
104 bool "Tegra20 family"
Tom Rini8dda2e22017-03-07 07:13:42 -0500105 select ARM_ERRATA_716044
106 select ARM_ERRATA_742230
107 select ARM_ERRATA_751472
Tom Warren56079ec2015-07-17 08:12:51 -0700108 select TEGRA_ARMV7_COMMON
Masahiro Yamadaddd960e2014-08-31 07:10:56 +0900109
110config TEGRA30
111 bool "Tegra30 family"
Tom Rini8dda2e22017-03-07 07:13:42 -0500112 select ARM_ERRATA_743622
113 select ARM_ERRATA_751472
Tom Warren56079ec2015-07-17 08:12:51 -0700114 select TEGRA_ARMV7_COMMON
Masahiro Yamadaddd960e2014-08-31 07:10:56 +0900115
116config TEGRA114
117 bool "Tegra114 family"
Tom Warren56079ec2015-07-17 08:12:51 -0700118 select TEGRA_ARMV7_COMMON
Masahiro Yamadaddd960e2014-08-31 07:10:56 +0900119
120config TEGRA124
121 bool "Tegra124 family"
Tom Warren56079ec2015-07-17 08:12:51 -0700122 select TEGRA_ARMV7_COMMON
Simon Glass66de3ee2017-07-25 08:29:58 -0600123 imply REGMAP
124 imply SYSCON
Masahiro Yamadaddd960e2014-08-31 07:10:56 +0900125
Tom Warren7aaa5a62015-03-04 16:36:00 -0700126config TEGRA210
127 bool "Tegra210 family"
Stephen Warren15bcc622015-11-23 10:32:01 -0700128 select TEGRA_ARMV8_COMMON
Thierry Redingb64e0b92019-04-15 11:32:18 +0200129 select TEGRA_CLKRST
Michal Simek5ed063d2018-07-23 15:55:13 +0200130 select TEGRA_GPIO
Thierry Reding9e578192019-04-15 11:32:19 +0200131 select TEGRA_GP_PADCTRL
Thierry Reding1a869c72019-04-15 11:32:20 +0200132 select TEGRA_MC
Stephen Warren140a9ea2016-09-13 10:46:00 -0600133 select TEGRA_NO_BPMP
Thierry Reding07ea02b2019-04-15 11:32:21 +0200134 select TEGRA_PINCTRL
Thierry Redinge19143b2019-04-15 11:32:22 +0200135 select TEGRA_PMC
Thierry Redingf9ec2ec2019-04-15 11:32:25 +0200136 select TEGRA_PMC_SECURE
Tom Warren7aaa5a62015-03-04 16:36:00 -0700137
Stephen Warrenc7ba99c2016-05-12 13:32:55 -0600138config TEGRA186
139 bool "Tegra186 family"
Stephen Warren0f67e232016-06-17 09:43:57 -0600140 select DM_MAILBOX
Stephen Warren73dd5c42016-08-08 09:41:34 -0600141 select TEGRA186_BPMP
Stephen Warrend9fd7002016-08-08 11:28:24 -0600142 select TEGRA186_CLOCK
Stephen Warrenc7ba99c2016-05-12 13:32:55 -0600143 select TEGRA186_GPIO
Stephen Warren4dd99d12016-08-08 11:28:25 -0600144 select TEGRA186_RESET
Stephen Warrenc7ba99c2016-05-12 13:32:55 -0600145 select TEGRA_ARMV8_COMMON
Stephen Warren0f67e232016-06-17 09:43:57 -0600146 select TEGRA_HSP
Stephen Warren49626ea2016-07-18 12:17:11 -0600147 select TEGRA_IVC
Stephen Warrenc7ba99c2016-05-12 13:32:55 -0600148
Masahiro Yamadaddd960e2014-08-31 07:10:56 +0900149endchoice
150
Stephen Warrendd8204d2016-01-26 10:59:42 -0700151config TEGRA_DISCONNECT_UDC_ON_BOOT
152 bool "Disconnect USB device mode controller on boot"
Thierry Reding836a56e2019-04-15 11:32:26 +0200153 depends on CI_UDC
Stephen Warrendd8204d2016-01-26 10:59:42 -0700154 default y
155 help
156 When loading U-Boot into RAM over USB protocols using tools such as
157 tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
158 mode controller is initialized and enumerated by the host PC running
159 the tool. Unfortunately, these tools do not shut down the USB
160 controller before executing the downloaded code, and so the host PC
161 does not "de-enumerate" the USB device. This option shuts down the
162 USB controller when U-Boot boots to avoid leaving a stale USB device
163 present.
164
Simon Glassb724bd72015-02-11 16:32:59 -0700165config SYS_MALLOC_F_LEN
166 default 0x1800
167
Masahiro Yamada09f455d2015-02-20 17:04:04 +0900168source "arch/arm/mach-tegra/tegra20/Kconfig"
169source "arch/arm/mach-tegra/tegra30/Kconfig"
170source "arch/arm/mach-tegra/tegra114/Kconfig"
171source "arch/arm/mach-tegra/tegra124/Kconfig"
Tom Warren7aaa5a62015-03-04 16:36:00 -0700172source "arch/arm/mach-tegra/tegra210/Kconfig"
Stephen Warrenc7ba99c2016-05-12 13:32:55 -0600173source "arch/arm/mach-tegra/tegra186/Kconfig"
Masahiro Yamadaddd960e2014-08-31 07:10:56 +0900174
Simon Glass42e6f852017-05-17 03:25:11 -0600175config CMD_ENTERRCM
176 bool "Enable 'enterrcm' command"
177 default y
178 help
179 Tegra's boot ROM supports a mode whereby code may be downloaded and
180 flash-programmed over a USB connection. On dev boards, this is
181 typically entered by holding down a "force recovery" button and
182 resetting the CPU. However, not all boards have such a button (one
183 example is the Compulab Trimslice), so a method to enter RCM from
184 software is useful.
185
186 Even on boards other than Trimslice, controlling this over a UART
187 may be useful, e.g. to allow simple remote control without the need
188 for mechanical button actuators, or hooking up relays/... to the
189 button.
190
Masahiro Yamadaddd960e2014-08-31 07:10:56 +0900191endif