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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / f77b5a4cd1365bdb7bb6e108db374bb1c68b6f9f / . / drivers / clk / renesas / r8a77995-cpg-mssr.c
blob: a4e289e3293d37e9aa3b0eb583a62099b2e43c47 [file] [log] [blame]
Marek Vasutf77b5a42018-01-08 14:01:40 +0100[diff] [blame^]1/*
2 * Renesas R8A77995 CPG MSSR driver
3 *
4 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
8 *
9 * Copyright (C) 2016 Glider bvba
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#include <common.h>
15#include <clk-uclass.h>
16#include <dm.h>
17
18#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
19
20#include "renesas-cpg-mssr.h"
21
22static const struct cpg_core_clk r8a77995_core_clks[] = {
23 /* External Clock Inputs */
24 DEF_INPUT("extal", CLK_EXTAL),
25
26 /* Internal Core Clocks */
27 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
28 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
29 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
30
31 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
32 DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
33 DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
34 DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
35 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
36 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
37 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
38 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
39 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
40 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
41 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
42
43 /* Core Clock Outputs */
44 DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
45 DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
46 DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
47 DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
48 DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
49 DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
50 DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
51 DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
52 DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
53 DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
54 DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
55 DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
56 DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
57 DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
58
59 DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
60 DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
61 DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
62 DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
63
64 DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
65 DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
66 DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
67 DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
68
69 DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
70};
71
72static const struct mssr_mod_clk r8a77995_mod_clks[] = {
73 DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
74 DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
75 DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
76 DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
77 DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
78 DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
79 DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
80 DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
81 DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
82 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
83 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
84 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
85 DEF_MOD("cmt3", 300, R8A77995_CLK_R),
86 DEF_MOD("cmt2", 301, R8A77995_CLK_R),
87 DEF_MOD("cmt1", 302, R8A77995_CLK_R),
88 DEF_MOD("cmt0", 303, R8A77995_CLK_R),
89 DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
90 DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
91 DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
92 DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
93 DEF_MOD("rwdt", 402, R8A77995_CLK_R),
94 DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
95 DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
96 DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
97 DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
98 DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
99 DEF_MOD("thermal", 522, R8A77995_CLK_CP),
100 DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
101 DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
102 DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
103 DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
104 DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
105 DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
106 DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
107 DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
108 DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
109 DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
110 DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
111 DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
112 DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
113 DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
114 DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
115 DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
116 DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
117 DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
118 DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
119 DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
120 DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
121 DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
122 DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
123 DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
124 DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
125 DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
126 DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
127 DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
128 DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
129 DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
130 DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
131 DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
132 DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
133 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
134 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
135 DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
136 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
137 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
138 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
139 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
140 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
141 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
142};
143
144static const struct mstp_stop_table r8a77995_mstp_table[] = {
145 { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
146 { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
147 { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
148 { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
149 { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
150 { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
151};
152
153static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
154 .core_clk = r8a77995_core_clks,
155 .core_clk_size = ARRAY_SIZE(r8a77995_core_clks),
156 .mod_clk = r8a77995_mod_clks,
157 .mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks),
158 .mstp_table = r8a77995_mstp_table,
159 .mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
160 .reset_node = "renesas,r8a77995-rst",
161};
162
163static const struct udevice_id r8a77995_clk_ids[] = {
164 {
165 .compatible = "renesas,r8a77995-cpg-mssr",
166 .data = (ulong)&r8a77995_cpg_mssr_info
167 },
168 { }
169};
170
171U_BOOT_DRIVER(clk_r8a77995) = {
172 .name = "clk_r8a77995",
173 .id = UCLASS_CLK,
174 .of_match = r8a77995_clk_ids,
175 .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
176 .ops = &gen3_clk_ops,
177 .probe = gen3_clk_probe,
178 .remove = gen3_clk_remove,
179};