blob: 5c41a1c40a667513ce8b1828227f29c291ecac39 [file] [log] [blame]
wdenk507bbe32004-04-18 21:13:41 +00001/*
Michal Simek53ea9812008-07-11 10:10:31 +02002 * (C) Copyright 2008 Michal Simek <monstr@monstr.eu>
3 * Clean driver and add xilinx constant from header file
wdenk507bbe32004-04-18 21:13:41 +00004 *
Michal Simek53ea9812008-07-11 10:10:31 +02005 * (C) Copyright 2004 Atmark Techno, Inc.
wdenk507bbe32004-04-18 21:13:41 +00006 * Yasushi SHOJI <yashi@atmark-techno.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Michal Simek53ea9812008-07-11 10:10:31 +020018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk507bbe32004-04-18 21:13:41 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <config.h>
Michal Simek53ea9812008-07-11 10:10:31 +020028#include <asm/io.h>
wdenke35745b2004-04-18 23:32:11 +000029
Michal Simek0731cba2007-09-24 00:25:11 +020030#ifdef CONFIG_XILINX_UARTLITE
wdenke35745b2004-04-18 23:32:11 +000031
Michal Simek53ea9812008-07-11 10:10:31 +020032#define RX_FIFO_OFFSET 0 /* receive FIFO, read only */
33#define TX_FIFO_OFFSET 4 /* transmit FIFO, write only */
34#define STATUS_REG_OFFSET 8 /* status register, read only */
wdenk507bbe32004-04-18 21:13:41 +000035
Michal Simek53ea9812008-07-11 10:10:31 +020036#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
37#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
38#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
wdenk507bbe32004-04-18 21:13:41 +000039
Michal Simek53ea9812008-07-11 10:10:31 +020040#define UARTLITE_STATUS (CONFIG_SERIAL_BASE + STATUS_REG_OFFSET)
41#define UARTLITE_TX_FIFO (CONFIG_SERIAL_BASE + TX_FIFO_OFFSET)
42#define UARTLITE_RX_FIFO (CONFIG_SERIAL_BASE + RX_FIFO_OFFSET)
wdenk507bbe32004-04-18 21:13:41 +000043
44int serial_init(void)
45{
46 /* FIXME: Nothing for now. We should initialize fifo, etc */
47 return 0;
48}
49
50void serial_setbrg(void)
51{
52 /* FIXME: what's this for? */
53}
54
55void serial_putc(const char c)
56{
Michal Simek53ea9812008-07-11 10:10:31 +020057 if (c == '\n')
58 serial_putc('\r');
59 while (in_be32(UARTLITE_STATUS) & SR_TX_FIFO_FULL);
60 out_be32(UARTLITE_TX_FIFO, (unsigned char) (c & 0xff));
wdenk507bbe32004-04-18 21:13:41 +000061}
62
63void serial_puts(const char * s)
64{
65 while (*s) {
66 serial_putc(*s++);
67 }
68}
69
70int serial_getc(void)
71{
Michal Simek53ea9812008-07-11 10:10:31 +020072 while (!(in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA));
73 return in_be32(UARTLITE_RX_FIFO) & 0xff;
wdenk507bbe32004-04-18 21:13:41 +000074}
75
76int serial_tstc(void)
77{
Michal Simek53ea9812008-07-11 10:10:31 +020078 return (in_be32(UARTLITE_STATUS) & SR_RX_FIFO_VALID_DATA);
wdenk507bbe32004-04-18 21:13:41 +000079}
wdenke35745b2004-04-18 23:32:11 +000080
81#endif /* CONFIG_MICROBLZE */