blob: 55b9a5eb8a5d4e3e4cd332e95d0d70508572f0a0 [file] [log] [blame]
Tom Riniba1ed5b2021-12-14 13:36:35 -05001config ARCH_MAP_SYSMEM
Tom Rini11232132022-04-06 09:21:25 -04002 depends on SANDBOX
Tom Riniba1ed5b2021-12-14 13:36:35 -05003 def_bool y
4
Masahiro Yamadaa350c6a2015-07-15 20:59:29 +09005config CREATE_ARCH_SYMLINK
6 bool
7
Masahiro Yamada9a387122016-06-28 10:48:42 +09008config HAVE_ARCH_IOREMAP
9 bool
10
Tom Riniab92b382021-08-26 11:47:59 -040011config SYS_CACHE_SHIFT_4
12 bool
13
14config SYS_CACHE_SHIFT_5
15 bool
16
17config SYS_CACHE_SHIFT_6
18 bool
19
20config SYS_CACHE_SHIFT_7
21 bool
22
23config SYS_CACHELINE_SIZE
24 int
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
29 # Fall-back for MIPS
30 default 32 if MIPS
31
Simon Glass0b2fa982020-12-16 21:20:06 -070032config LINKER_LIST_ALIGN
33 int
34 default 32 if SANDBOX
35 default 8 if ARM64 || X86
36 default 4
37 help
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
42
Masahiro Yamada51631252014-07-30 14:08:15 +090043choice
44 prompt "Architecture select"
45 default SANDBOX
46
47config ARC
48 bool "ARC architecture"
Michal Simek5ed063d2018-07-23 15:55:13 +020049 select ARC_TIMER
50 select CLK
Michal Simek7b564322020-08-19 10:44:20 +020051 select DM
Alexey Brodkina67ef282015-02-03 13:58:20 +030052 select HAVE_PRIVATE_LIBGCC
Alexey Brodkin01496c42015-03-17 14:55:14 +030053 select SUPPORT_OF_CONTROL
Tom Riniab92b382021-08-26 11:47:59 -040054 select SYS_CACHE_SHIFT_7
Vlad Zakharov3daa7c72017-03-21 14:49:49 +030055 select TIMER
Tom Rini83505a72022-07-31 21:08:23 -040056 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
57 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
Masahiro Yamada51631252014-07-30 14:08:15 +090058
59config ARM
60 bool "ARM architecture"
Marek Behún8f969652021-05-20 13:24:22 +020061 select ARCH_SUPPORTS_LTO
Masahiro Yamadaa350c6a2015-07-15 20:59:29 +090062 select CREATE_ARCH_SYMLINK
Masahiro Yamada64b77ed2015-07-03 16:13:09 +090063 select HAVE_PRIVATE_LIBGCC if !ARM64
Simon Glass01537232021-12-01 09:02:38 -070064 select SUPPORT_ACPI
Masahiro Yamada783e6a72014-09-22 19:59:05 +090065 select SUPPORT_OF_CONTROL
Masahiro Yamada51631252014-07-30 14:08:15 +090066
Masahiro Yamada51631252014-07-30 14:08:15 +090067config M68K
68 bool "M68000 architecture"
angelo@sysam.it6463fd82015-12-06 17:47:59 +010069 select HAVE_PRIVATE_LIBGCC
Angelo Dureghello1e483922023-02-07 23:45:03 +010070 select USE_PRIVATE_LIBGCC
Michal Simek35b7ca72020-11-04 15:33:20 +010071 select NEEDS_MANUAL_RELOC
Derald D. Woods405fc832018-01-22 17:17:10 -060072 select SYS_BOOT_GET_CMDLINE
73 select SYS_BOOT_GET_KBD
Tom Riniab92b382021-08-26 11:47:59 -040074 select SYS_CACHE_SHIFT_4
Angelo Dureghelloabe0f872019-03-13 21:46:51 +010075 select SUPPORT_OF_CONTROL
Masahiro Yamada51631252014-07-30 14:08:15 +090076
77config MICROBLAZE
78 bool "MicroBlaze architecture"
Masahiro Yamada783e6a72014-09-22 19:59:05 +090079 select SUPPORT_OF_CONTROL
Michal Simeka36d8672022-06-24 14:16:32 +020080 imply CMD_TIMER
81 imply SPL_REGMAP if SPL
82 imply SPL_TIMER if SPL
83 imply TIMER
84 imply XILINX_TIMER
Masahiro Yamada51631252014-07-30 14:08:15 +090085
86config MIPS
87 bool "MIPS architecture"
Masahiro Yamada9a387122016-06-28 10:48:42 +090088 select HAVE_ARCH_IOREMAP
Masahiro Yamada45ccec82014-10-24 01:30:43 +090089 select HAVE_PRIVATE_LIBGCC
Daniel Schwierzeck0fc13a92015-12-19 20:20:48 +010090 select SUPPORT_OF_CONTROL
Sean Anderson1dd56db2022-04-12 10:59:04 -040091 select SPL_SEPARATE_BSS if SPL
Masahiro Yamada51631252014-07-30 14:08:15 +090092
Masahiro Yamada51631252014-07-30 14:08:15 +090093config NIOS2
94 bool "Nios II architecture"
Thomas Choubcae80e2015-10-21 21:34:57 +080095 select CPU
Michal Simek5ed063d2018-07-23 15:55:13 +020096 select DM
Tom Rini448e2b62023-01-16 15:46:49 -050097 select DM_EVENT
Michal Simek5ed063d2018-07-23 15:55:13 +020098 select OF_CONTROL
99 select SUPPORT_OF_CONTROL
Michal Simek08a00cb2018-07-23 15:55:14 +0200100 imply CMD_DM
Masahiro Yamada51631252014-07-30 14:08:15 +0900101
Masahiro Yamada51631252014-07-30 14:08:15 +0900102config PPC
103 bool "PowerPC architecture"
Masahiro Yamada45ccec82014-10-24 01:30:43 +0900104 select HAVE_PRIVATE_LIBGCC
Simon Glassc1c61572015-02-07 11:51:35 -0700105 select SUPPORT_OF_CONTROL
Derald D. Woods405fc832018-01-22 17:17:10 -0600106 select SYS_BOOT_GET_CMDLINE
107 select SYS_BOOT_GET_KBD
Masahiro Yamada51631252014-07-30 14:08:15 +0900108
Rick Chen068feb92017-12-26 13:55:58 +0800109config RISCV
Bin Meng117a4332018-09-26 06:55:06 -0700110 bool "RISC-V architecture"
Anup Patel7c8d2102019-02-25 08:14:04 +0000111 select CREATE_ARCH_SYMLINK
Rick Chen068feb92017-12-26 13:55:58 +0800112 select SUPPORT_OF_CONTROL
Bin Mengbf6cc822018-09-26 06:55:19 -0700113 select OF_CONTROL
114 select DM
Tom Rini448e2b62023-01-16 15:46:49 -0500115 select DM_EVENT
Zong Li57b99002022-11-16 07:08:39 +0000116 imply SPL_SEPARATE_BSS if SPL
Bin Mengcd1f45c2018-09-26 06:55:20 -0700117 imply DM_SERIAL
Bin Mengcd1f45c2018-09-26 06:55:20 -0700118 imply DM_MMC
119 imply DM_SPI
120 imply DM_SPI_FLASH
121 imply BLK
122 imply CLK
123 imply MTD
124 imply TIMER
Bin Mengbf6cc822018-09-26 06:55:19 -0700125 imply CMD_DM
Lukas Auer8c59f202019-08-21 21:14:45 +0200126 imply SPL_DM
127 imply SPL_OF_CONTROL
128 imply SPL_LIBCOMMON_SUPPORT
129 imply SPL_LIBGENERIC_SUPPORT
Simon Glass2a736062021-08-08 12:20:12 -0600130 imply SPL_SERIAL
Lukas Auer8c59f202019-08-21 21:14:45 +0200131 imply SPL_TIMER
Rick Chen068feb92017-12-26 13:55:58 +0800132
Masahiro Yamada51631252014-07-30 14:08:15 +0900133config SANDBOX
134 bool "Sandbox"
Marek Behún94bb8912021-05-20 13:24:07 +0200135 select ARCH_SUPPORTS_LTO
Tom Rinie5ec4812017-01-22 19:43:11 -0500136 select BOARD_LATE_INIT
Michael Walleefc06442020-05-22 14:07:38 +0200137 select BZIP2
Heinrich Schuchardtb1ad4152020-10-27 20:29:22 +0100138 select CMD_POWEROFF
Masahiro Yamada58d423b2015-03-31 12:47:53 +0900139 select DM
Tom Rini448e2b62023-01-16 15:46:49 -0500140 select DM_EVENT
Andrew Scull0518e7a2022-05-30 10:00:12 +0000141 select DM_FUZZING_ENGINE
Masahiro Yamada58d423b2015-03-31 12:47:53 +0900142 select DM_GPIO
Michal Simek5ed063d2018-07-23 15:55:13 +0200143 select DM_I2C
144 select DM_KEYBOARD
Simon Glass9a46bd32016-06-12 23:30:26 -0600145 select DM_MMC
Michal Simek5ed063d2018-07-23 15:55:13 +0200146 select DM_SERIAL
147 select DM_SPI
148 select DM_SPI_FLASH
Michael Walleefc06442020-05-22 14:07:38 +0200149 select GZIP_COMPRESSED
Tom Rini68e54042022-11-19 18:45:23 -0500150 select IO_TRACE
Tom Rinid56b4b12017-07-22 18:36:16 -0400151 select LZO
Heinrich Schuchardt1c0bc802020-03-14 12:13:40 +0100152 select OF_BOARD_SETUP
Ramon Friedbb413332019-04-27 11:15:23 +0300153 select PCI_ENDPOINT
Michal Simek5ed063d2018-07-23 15:55:13 +0200154 select SPI
155 select SUPPORT_OF_CONTROL
Heinrich Schuchardtb1ad4152020-10-27 20:29:22 +0100156 select SYSRESET_CMD_POWEROFF
Tom Riniab92b382021-08-26 11:47:59 -0400157 select SYS_CACHE_SHIFT_4
Wasim Khan57c675d2021-03-08 16:48:16 +0100158 select IRQ
Kory Maincent95300f22021-05-04 19:31:23 +0200159 select SUPPORT_EXTENSION_SCAN
Simon Glasse1722fc2021-12-01 09:02:36 -0700160 select SUPPORT_ACPI
Bin Meng0f1caa92018-08-02 23:58:03 -0700161 imply BITREVERSE
Simon Glass919e7a82018-11-15 18:43:53 -0700162 select BLOBLIST
Marek Behún1b457e72021-05-20 13:24:08 +0200163 imply LTO
Michal Simek08a00cb2018-07-23 15:55:14 +0200164 imply CMD_DM
Heinrich Schuchardt6ca5ff32020-11-12 00:29:59 +0100165 imply CMD_EXCEPTION
Simon Glassded48cd2017-05-17 03:25:44 -0600166 imply CMD_GETTIME
Simon Glass551c3932017-05-17 03:25:25 -0600167 imply CMD_HASH
Simon Glass594e8d12017-05-17 03:25:34 -0600168 imply CMD_IO
Simon Glass7d0f5c12017-05-17 03:25:36 -0600169 imply CMD_IOTRACE
Simon Glassee7c0e72017-05-17 03:25:43 -0600170 imply CMD_LZMADEC
Tom Rinia4298dd2019-05-29 17:01:28 -0400171 imply CMD_SF
Michal Simek5ed063d2018-07-23 15:55:13 +0200172 imply CMD_SF_TEST
Tom Rini91d27a12017-06-02 11:03:50 -0400173 imply CRC32_VERIFY
174 imply FAT_WRITE
Rajan Vaja31b82172018-09-19 03:43:46 -0700175 imply FIRMWARE
Andrew Scull0518e7a2022-05-30 10:00:12 +0000176 imply FUZZING_ENGINE_SANDBOX
Daniel Thompson221a9492017-05-19 17:26:58 +0100177 imply HASH_VERIFY
Tom Rini91d27a12017-06-02 11:03:50 -0400178 imply LZMA
Jens Wiklanderfe39e8e2018-09-25 16:40:17 +0200179 imply TEE
Jens Wiklander0a60a812018-09-25 16:40:23 +0200180 imply AVB_VERIFY
181 imply LIBAVB
182 imply CMD_AVB
Heinrich Schuchardtd3adee12022-01-16 13:04:06 +0100183 imply PARTITION_TYPE_GUID
Igor Opaniuk7c591a82021-02-14 16:27:27 +0100184 imply SCP03
185 imply CMD_SCP03
Jens Wiklander0a60a812018-09-25 16:40:23 +0200186 imply UDP_FUNCTION_FASTBOOT
Bin Meng4f89d492018-10-15 02:21:26 -0700187 imply VIRTIO_MMIO
188 imply VIRTIO_PCI
189 imply VIRTIO_SANDBOX
190 imply VIRTIO_BLK
191 imply VIRTIO_NET
Simon Glass2a049572018-12-10 10:37:31 -0700192 imply DM_SOUND
Ramon Friedbb413332019-04-27 11:15:23 +0300193 imply PCI_SANDBOX_EP
Simon Glassc8821632019-02-16 20:24:49 -0700194 imply PCH
Alex Margineanec9594a2019-06-03 19:12:28 +0300195 imply PHYLIB
196 imply DM_MDIO
Alex Margineanc3d9f3f2019-07-12 10:13:53 +0300197 imply DM_MDIO_MUX
Simon Glass3b65ee32019-12-06 21:41:54 -0700198 imply ACPI_PMC
199 imply ACPI_PMC_SANDBOX
200 imply CMD_PMC
John Chau4a4830c2020-07-02 12:01:21 +0800201 imply CMD_CLONE
Simon Glassf158ba12020-11-05 10:33:38 -0700202 imply SILENT_CONSOLE
Simon Glass51bb3382020-11-05 10:33:48 -0700203 imply BOOTARGS_SUBST
Claudiu Manoilff98da02021-03-14 20:14:57 +0800204 imply PHY_FIXED
205 imply DM_DSA
Kory Maincent95300f22021-05-04 19:31:23 +0200206 imply CMD_EXTENSION
Simon Glass93e1edf2021-11-24 09:26:44 -0700207 imply KEYBOARD
Simon Glass6405ab72021-11-24 09:26:42 -0700208 imply PHYSMEM
Simon Glass437992d2021-12-01 09:02:43 -0700209 imply GENERATE_ACPI_TABLE
Philippe Reynes059df562022-03-28 22:56:53 +0200210 imply BINMAN
Masahiro Yamada51631252014-07-30 14:08:15 +0900211
212config SH
213 bool "SuperH architecture"
Masahiro Yamada45ccec82014-10-24 01:30:43 +0900214 select HAVE_PRIVATE_LIBGCC
Marek Vasut8c2c4632019-08-31 18:27:58 +0200215 select SUPPORT_OF_CONTROL
Masahiro Yamada51631252014-07-30 14:08:15 +0900216
Masahiro Yamada51631252014-07-30 14:08:15 +0900217config X86
218 bool "x86 architecture"
Simon Glass98987902019-04-25 21:58:45 -0600219 select SUPPORT_SPL
220 select SUPPORT_TPL
Masahiro Yamadaa350c6a2015-07-15 20:59:29 +0900221 select CREATE_ARCH_SYMLINK
Masahiro Yamada58d423b2015-03-31 12:47:53 +0900222 select DM
Bin Meng3bf9a8e2018-10-15 02:21:16 -0700223 select HAVE_ARCH_IOMAP
Michal Simek5ed063d2018-07-23 15:55:13 +0200224 select HAVE_PRIVATE_LIBGCC
225 select OF_CONTROL
Bin Meng4f0faac2017-07-30 06:23:16 -0700226 select PCI
Simon Glasse1722fc2021-12-01 09:02:36 -0700227 select SUPPORT_ACPI
Michal Simek5ed063d2018-07-23 15:55:13 +0200228 select SUPPORT_OF_CONTROL
Tom Riniab92b382021-08-26 11:47:59 -0400229 select SYS_CACHE_SHIFT_6
Bin Meng0ce9c572017-07-30 06:23:07 -0700230 select TIMER
Michal Simek5ed063d2018-07-23 15:55:13 +0200231 select USE_PRIVATE_LIBGCC
Bin Meng0ce9c572017-07-30 06:23:07 -0700232 select X86_TSC_TIMER
Wasim Khan543d0912021-03-08 16:48:15 +0100233 select IRQ
Simon Glassbcd4e6f2020-07-19 13:55:52 -0600234 imply HAS_ROM if X86_RESET_VECTOR
Bin Meng24357df2017-07-30 19:24:02 -0700235 imply BLK
Michal Simek08a00cb2018-07-23 15:55:14 +0200236 imply CMD_DM
Simon Glassfe7604a2017-05-17 03:25:21 -0600237 imply CMD_FPGA_LOADMK
Simon Glassd91a9d72017-05-17 03:25:23 -0600238 imply CMD_GETTIME
Simon Glass594e8d12017-05-17 03:25:34 -0600239 imply CMD_IO
Simon Glass1b330892017-05-17 03:25:39 -0600240 imply CMD_IRQ
Bin Mengc11b17c2017-08-16 05:46:49 -0700241 imply CMD_PCI
Tom Rinia4298dd2019-05-29 17:01:28 -0400242 imply CMD_SF
Simon Glass719d36e2017-08-04 16:34:46 -0600243 imply CMD_SF_TEST
Simon Glasse7a815f2017-08-04 16:35:03 -0600244 imply CMD_ZBOOT
Michal Simek5ed063d2018-07-23 15:55:13 +0200245 imply DM_GPIO
246 imply DM_KEYBOARD
247 imply DM_MMC
248 imply DM_RTC
249 imply DM_SCSI
250 imply DM_SERIAL
251 imply DM_SPI
252 imply DM_SPI_FLASH
253 imply DM_USB
Simon Glassb86986c2022-10-18 07:46:31 -0600254 imply VIDEO
Michal Simek5ed063d2018-07-23 15:55:13 +0200255 imply SYSRESET
Kever Yang09259fc2019-04-02 20:41:25 +0800256 imply SPL_SYSRESET
Michal Simek5ed063d2018-07-23 15:55:13 +0200257 imply SYSRESET_X86
Chris Packhamf58ad982017-08-28 20:50:46 +1200258 imply USB_ETHER_ASIX
259 imply USB_ETHER_SMSC95XX
Michal Simek5ed063d2018-07-23 15:55:13 +0200260 imply USB_HOST_ETHER
Simon Glassc8821632019-02-16 20:24:49 -0700261 imply PCH
Simon Glass6405ab72021-11-24 09:26:42 -0700262 imply PHYSMEM
Simon Glass31d52612019-05-02 10:52:24 -0600263 imply RTC_MC146818
Simon Glass27ba6282021-12-01 09:02:39 -0700264 imply ACPIGEN if !QEMU && !EFI_APP
Simon Glass839d66c2020-11-05 06:32:17 -0700265 imply SYSINFO if GENERATE_SMBIOS_TABLE
266 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
Simon Glassd6b318d2021-12-18 11:27:50 -0700267 imply TIMESTAMP
Masahiro Yamada51631252014-07-30 14:08:15 +0900268
Simon Glass98987902019-04-25 21:58:45 -0600269 # Thing to enable for when SPL/TPL are enabled: SPL
270 imply SPL_DM
271 imply SPL_OF_LIBFDT
Simon Glass9ca00682021-07-10 21:14:31 -0600272 imply SPL_DRIVERS_MISC
Simon Glass83061db2021-07-10 21:14:30 -0600273 imply SPL_GPIO
Simon Glasse556d3d2019-12-06 21:42:51 -0700274 imply SPL_PINCTRL
Simon Glass98987902019-04-25 21:58:45 -0600275 imply SPL_LIBCOMMON_SUPPORT
276 imply SPL_LIBGENERIC_SUPPORT
Simon Glass2a736062021-08-08 12:20:12 -0600277 imply SPL_SERIAL
Simon Glass98987902019-04-25 21:58:45 -0600278 imply SPL_SPI_FLASH_SUPPORT
Simon Glassea2ca7e2021-08-08 12:20:14 -0600279 imply SPL_SPI
Simon Glass98987902019-04-25 21:58:45 -0600280 imply SPL_OF_CONTROL
281 imply SPL_TIMER
282 imply SPL_REGMAP
283 imply SPL_SYSCON
284 # TPL
285 imply TPL_DM
Simon Glass9ca00682021-07-10 21:14:31 -0600286 imply TPL_DRIVERS_MISC
Simon Glass83061db2021-07-10 21:14:30 -0600287 imply TPL_GPIO
Simon Glasse556d3d2019-12-06 21:42:51 -0700288 imply TPL_PINCTRL
Simon Glass98987902019-04-25 21:58:45 -0600289 imply TPL_LIBCOMMON_SUPPORT
290 imply TPL_LIBGENERIC_SUPPORT
Simon Glass2a736062021-08-08 12:20:12 -0600291 imply TPL_SERIAL
Simon Glass98987902019-04-25 21:58:45 -0600292 imply TPL_OF_CONTROL
293 imply TPL_TIMER
294 imply TPL_REGMAP
295 imply TPL_SYSCON
296
Chris Zankelc978b522016-08-10 18:36:44 +0300297config XTENSA
298 bool "Xtensa architecture"
299 select CREATE_ARCH_SYMLINK
300 select SUPPORT_OF_CONTROL
301
Masahiro Yamada51631252014-07-30 14:08:15 +0900302endchoice
303
Masahiro Yamada3174e4e2014-09-14 03:01:48 +0900304config SYS_ARCH
305 string
306 help
307 This option should contain the architecture name to build the
308 appropriate arch/<CONFIG_SYS_ARCH> directory.
309 All the architectures should specify this option correctly.
310
311config SYS_CPU
312 string
313 help
314 This option should contain the CPU name to build the correct
315 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
316
317 This is optional. For those targets without the CPU directory,
318 leave this option empty.
319
320config SYS_SOC
321 string
322 help
323 This option should contain the SoC name to build the directory
324 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
325
326 This is optional. For those targets without the SoC directory,
327 leave this option empty.
328
329config SYS_VENDOR
330 string
331 help
332 This option should contain the vendor name of the target board.
333 If it is set and
334 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
335 directory is compiled.
336 If CONFIG_SYS_BOARD is also set, the sources under
337 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
338
339 This is optional. For those targets without the vendor directory,
340 leave this option empty.
341
342config SYS_BOARD
343 string
344 help
345 This option should contain the name of the target board.
346 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
347 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
348 whether CONFIG_SYS_VENDOR is set or not.
349
350 This is optional. For those targets without the board directory,
351 leave this option empty.
352
353config SYS_CONFIG_NAME
354 string
355 help
356 This option should contain the base name of board header file.
357 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
358 should be included from include/config.h.
359
Vignesh Raghavendraadd49672019-04-22 21:43:32 +0530360config SYS_DISABLE_DCACHE_OPS
361 bool
362 help
363 This option disables dcache flush and dcache invalidation
364 operations. For example, on coherent systems where cache
365 operatios are not required, enable this option to avoid them.
366 Note that, its up to the individual architectures to implement
367 this functionality.
368
Tom Rinibe7dbb62021-12-12 22:12:30 -0500369config SYS_IMMR
Tom Rinidd2986a2022-03-30 09:30:15 -0400370 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
Tom Rinibe7dbb62021-12-12 22:12:30 -0500371 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
372 default 0xFF000000 if MPC8xx
373 default 0xF0000000 if ARCH_MPC8313
374 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
375 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
Pali Rohár39f42fe2022-05-02 18:29:25 +0200376 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
377 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
378 ARCH_P2020
Tom Rinibe7dbb62021-12-12 22:12:30 -0500379 default SYS_CCSRBAR_DEFAULT
380 help
381 Address for the Internal Memory-Mapped Registers (IMMR) window used
382 to configure the features of many Freescale / NXP SoCs.
383
Tom Rinie52fca22022-12-02 16:42:36 -0500384config MONITOR_IS_IN_RAM
385 bool "U-Boot is loaded in to RAM by a pre-loader"
386 depends on M68K || NIOS2
387
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100388menu "Skipping low level initialization functions"
Tom Rini11232132022-04-06 09:21:25 -0400389 depends on ARM || MIPS || RISCV
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100390
391config SKIP_LOWLEVEL_INIT
392 bool "Skip calls to certain low level initialization functions"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400393 help
394 If enabled, then certain low level initializations (like setting up
395 the memory controller) are omitted and/or U-Boot does not relocate
396 itself into RAM.
397 Normally this variable MUST NOT be defined. The only exception is
398 when U-Boot is loaded (to RAM) by some other boot loader or by a
399 debugger which performs these initializations itself.
400
401config SPL_SKIP_LOWLEVEL_INIT
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100402 bool "Skip calls to certain low level initialization functions in SPL"
403 depends on SPL
Tom Rinia2ac2b92021-08-27 21:18:30 -0400404 help
405 If enabled, then certain low level initializations (like setting up
406 the memory controller) are omitted and/or U-Boot does not relocate
407 itself into RAM.
408 Normally this variable MUST NOT be defined. The only exception is
409 when U-Boot is loaded (to RAM) by some other boot loader or by a
410 debugger which performs these initializations itself.
411
412config TPL_SKIP_LOWLEVEL_INIT
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100413 bool "Skip calls to certain low level initialization functions in TPL"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400414 depends on SPL && ARM
415 help
416 If enabled, then certain low level initializations (like setting up
417 the memory controller) are omitted and/or U-Boot does not relocate
418 itself into RAM.
419 Normally this variable MUST NOT be defined. The only exception is
420 when U-Boot is loaded (to RAM) by some other boot loader or by a
421 debugger which performs these initializations itself.
422
423config SKIP_LOWLEVEL_INIT_ONLY
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100424 bool "Skip call to lowlevel_init during early boot ONLY"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400425 depends on ARM
426 help
427 This allows just the call to lowlevel_init() to be skipped. The
428 normal CP15 init (such as enabling the instruction cache) is still
429 performed.
430
431config SPL_SKIP_LOWLEVEL_INIT_ONLY
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100432 bool "Skip call to lowlevel_init during early SPL boot ONLY"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400433 depends on SPL && ARM
434 help
435 This allows just the call to lowlevel_init() to be skipped. The
436 normal CP15 init (such as enabling the instruction cache) is still
437 performed.
438
439config TPL_SKIP_LOWLEVEL_INIT_ONLY
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100440 bool "Skip call to lowlevel_init during early TPL boot ONLY"
Tom Rinia2ac2b92021-08-27 21:18:30 -0400441 depends on TPL && ARM
442 help
443 This allows just the call to lowlevel_init() to be skipped. The
444 normal CP15 init (such as enabling the instruction cache) is still
445 performed.
446
Heinrich Schuchardtc394e8d2022-12-30 19:41:28 +0100447endmenu
448
Tom Rini8c778f72022-10-28 20:27:10 -0400449config SYS_HAS_NONCACHED_MEMORY
450 bool "Enable reserving a non-cached memory area for drivers"
451 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
452 help
453 This is useful for drivers that would otherwise require a lot of
454 explicit cache maintenance. For some drivers it's also impossible to
455 properly maintain the cache. For example if the regions that need to
456 be flushed are not a multiple of the cache-line size, *and* padding
457 cannot be allocated between the regions to align them (i.e. if the
458 HW requires a contiguous array of regions, and the size of each
459 region is not cache-aligned), then a flush of one region may result
460 in overwriting data that hardware has written to another region in
461 the same cache-line. This can happen for example in network drivers
462 where descriptors for buffers are typically smaller than the CPU
463 cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
464
465config SYS_NONCACHED_MEMORY
466 hex "Size in bytes of the non-cached memory area"
467 depends on SYS_HAS_NONCACHED_MEMORY
468 default 0x100000
469 help
470 Size of non-cached memory area. This area of memory will be typically
471 located right below the malloc() area and mapped uncached in the MMU.
472
Masahiro Yamada51631252014-07-30 14:08:15 +0900473source "arch/arc/Kconfig"
474source "arch/arm/Kconfig"
Masahiro Yamada51631252014-07-30 14:08:15 +0900475source "arch/m68k/Kconfig"
476source "arch/microblaze/Kconfig"
477source "arch/mips/Kconfig"
Masahiro Yamada51631252014-07-30 14:08:15 +0900478source "arch/nios2/Kconfig"
Masahiro Yamada51631252014-07-30 14:08:15 +0900479source "arch/powerpc/Kconfig"
480source "arch/sandbox/Kconfig"
481source "arch/sh/Kconfig"
Masahiro Yamada51631252014-07-30 14:08:15 +0900482source "arch/x86/Kconfig"
Chris Zankelc978b522016-08-10 18:36:44 +0300483source "arch/xtensa/Kconfig"
Rick Chen068feb92017-12-26 13:55:58 +0800484source "arch/riscv/Kconfig"
Tom Rinic6c0e562022-03-23 17:19:55 -0400485
Tom Rinid622b082022-06-16 14:04:36 -0400486if ARM || M68K || PPC
487
488source "arch/Kconfig.nxp"
489
490endif
491
Tom Rinic6c0e562022-03-23 17:19:55 -0400492source "board/keymile/Kconfig"
Michal Simek89e81e62022-06-24 14:14:59 +0200493
Michal Simek10fd6d62022-06-24 14:14:59 +0200494if MIPS || MICROBLAZE
Michal Simek89e81e62022-06-24 14:14:59 +0200495
496choice
497 prompt "Endianness selection"
498 help
499 Some MIPS boards can be configured for either little or big endian
500 byte order. These modes require different U-Boot images. In general there
501 is one preferred byteorder for a particular system but some systems are
502 just as commonly used in the one or the other endianness.
503
504config SYS_BIG_ENDIAN
505 bool "Big endian"
Michal Simek10fd6d62022-06-24 14:14:59 +0200506 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
Michal Simek89e81e62022-06-24 14:14:59 +0200507
508config SYS_LITTLE_ENDIAN
509 bool "Little endian"
Michal Simek10fd6d62022-06-24 14:14:59 +0200510 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
Michal Simek89e81e62022-06-24 14:14:59 +0200511
512endchoice
513
514endif