wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 8 | * Alex Zuepke <azu@sysgo.de> |
| 9 | * |
| 10 | * See file CREDITS for list of people who contributed to this |
| 11 | * project. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * CPU specific code |
| 31 | */ |
| 32 | |
| 33 | #include <common.h> |
| 34 | #include <command.h> |
| 35 | |
| 36 | int cpu_init (void) |
| 37 | { |
| 38 | /* |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 39 | * setup up stacks if necessary |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 40 | */ |
| 41 | #ifdef CONFIG_USE_IRQ |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 42 | DECLARE_GLOBAL_DATA_PTR; |
| 43 | |
| 44 | IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4; |
| 45 | FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 46 | #endif |
wdenk | a8c7c70 | 2003-12-06 19:49:23 +0000 | [diff] [blame] | 47 | return 0; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | int cleanup_before_linux (void) |
| 51 | { |
| 52 | /* |
| 53 | * this function is called just before we call linux |
| 54 | * it prepares the processor for linux |
| 55 | * |
| 56 | * just disable everything that can disturb booting linux |
| 57 | */ |
| 58 | |
| 59 | unsigned long i; |
| 60 | |
| 61 | disable_interrupts (); |
| 62 | |
| 63 | /* turn off I-cache */ |
| 64 | asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
| 65 | i &= ~0x1000; |
| 66 | asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); |
| 67 | |
| 68 | /* flush I-cache */ |
| 69 | asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); |
| 70 | |
| 71 | return (0); |
| 72 | } |
| 73 | |
| 74 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
| 75 | { |
| 76 | extern void reset_cpu (ulong addr); |
| 77 | |
| 78 | printf ("resetting ...\n"); |
| 79 | |
| 80 | udelay (50000); /* wait 50 ms */ |
| 81 | disable_interrupts (); |
| 82 | reset_cpu (0); |
| 83 | |
| 84 | /*NOTREACHED*/ |
| 85 | return (0); |
| 86 | } |
| 87 | |
| 88 | /* taken from blob */ |
| 89 | void icache_enable (void) |
| 90 | { |
| 91 | register u32 i; |
| 92 | |
| 93 | /* read control register */ |
| 94 | asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
| 95 | |
| 96 | /* set i-cache */ |
| 97 | i |= 0x1000; |
| 98 | |
| 99 | /* write back to control register */ |
| 100 | asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); |
| 101 | } |
| 102 | |
| 103 | void icache_disable (void) |
| 104 | { |
| 105 | register u32 i; |
| 106 | |
| 107 | /* read control register */ |
| 108 | asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
| 109 | |
| 110 | /* clear i-cache */ |
| 111 | i &= ~0x1000; |
| 112 | |
| 113 | /* write back to control register */ |
| 114 | asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); |
| 115 | |
| 116 | /* flush i-cache */ |
| 117 | asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); |
| 118 | } |
| 119 | |
| 120 | int icache_status (void) |
| 121 | { |
| 122 | register u32 i; |
| 123 | |
| 124 | /* read control register */ |
| 125 | asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
| 126 | |
| 127 | /* return bit */ |
| 128 | return (i & 0x1000); |
| 129 | } |
| 130 | |
| 131 | /* we will never enable dcache, because we have to setup MMU first */ |
| 132 | void dcache_enable (void) |
| 133 | { |
| 134 | return; |
| 135 | } |
| 136 | |
| 137 | void dcache_disable (void) |
| 138 | { |
| 139 | return; |
| 140 | } |
| 141 | |
| 142 | int dcache_status (void) |
| 143 | { |
| 144 | return 0; /* always off */ |
| 145 | } |