blob: 55d3ab6f44234407194ad3b4eb8fc2efa59fc9f7 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Heiko Schochere379c032014-07-18 06:07:22 +02002/*
3 * (C) Copyright 2014
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 *
6 * Based on:
7 * Copyright (C) 2012 Freescale Semiconductor, Inc.
8 *
9 * Author: Fabio Estevam <fabio.estevam@freescale.com>
Heiko Schochere379c032014-07-18 06:07:22 +020010 */
11
12#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/iomux.h>
15#include <asm/arch/mx6-pins.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090016#include <linux/errno.h>
Heiko Schochere379c032014-07-18 06:07:22 +020017#include <asm/gpio.h>
Stefano Babic552a8482017-06-29 10:16:06 +020018#include <asm/mach-imx/iomux-v3.h>
19#include <asm/mach-imx/boot_mode.h>
Stefano Babic552a8482017-06-29 10:16:06 +020020#include <asm/mach-imx/video.h>
Heiko Schochere379c032014-07-18 06:07:22 +020021#include <asm/arch/crm_regs.h>
Heiko Schochere379c032014-07-18 06:07:22 +020022#include <asm/io.h>
23#include <asm/arch/sys_proto.h>
Heiko Schocher621ff132019-12-01 11:23:19 +010024#include <bmp_logo.h>
Heiko Schocherccc75952019-12-01 11:23:12 +010025#include <dm/root.h>
Heiko Schocher0f1130b2019-12-01 11:23:11 +010026#include <env.h>
Heiko Schocherf7cf76f2019-12-01 11:23:23 +010027#include <i2c_eeprom.h>
28#include <i2c.h>
Heiko Schocher0f1130b2019-12-01 11:23:11 +010029#include <micrel.h>
Heiko Schocher5e654962019-12-01 11:23:18 +010030#include <miiphy.h>
Heiko Schocher621ff132019-12-01 11:23:19 +010031#include <lcd.h>
Heiko Schocherfc7e3cc2019-12-01 11:23:15 +010032#include <led.h>
Heiko Schocher621ff132019-12-01 11:23:19 +010033#include <splash.h>
34#include <video_fb.h>
Heiko Schochere379c032014-07-18 06:07:22 +020035
36DECLARE_GLOBAL_DATA_PTR;
37
Heiko Schocherccc75952019-12-01 11:23:12 +010038enum {
39 BOARD_TYPE_4 = 4,
40 BOARD_TYPE_7 = 7,
41};
42
43#define ARI_BT_4 "aristainetos2_4@2"
44#define ARI_BT_7 "aristainetos2_7@1"
45
Heiko Schocher0f1130b2019-12-01 11:23:11 +010046int board_phy_config(struct phy_device *phydev)
47{
48 /* control data pad skew - devaddr = 0x02, register = 0x04 */
49 ksz9031_phy_extended_write(phydev, 0x02,
50 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
51 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
52 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
53 ksz9031_phy_extended_write(phydev, 0x02,
54 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
55 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
56 /* tx data pad skew - devaddr = 0x02, register = 0x06 */
57 ksz9031_phy_extended_write(phydev, 0x02,
58 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
59 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
60 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
61 ksz9031_phy_extended_write(phydev, 0x02,
62 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
63 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
64
65 if (phydev->drv->config)
66 phydev->drv->config(phydev);
67
68 return 0;
69}
70
Heiko Schocher0f1130b2019-12-01 11:23:11 +010071static int rotate_logo_one(unsigned char *out, unsigned char *in)
72{
73 int i, j;
74
75 for (i = 0; i < BMP_LOGO_WIDTH; i++)
76 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
77 out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
78 in[i * BMP_LOGO_WIDTH + j];
79 return 0;
80}
81
82/*
83 * Rotate the BMP_LOGO (only)
84 * Will only work, if the logo is square, as
85 * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
86 */
87void rotate_logo(int rotations)
88{
89 unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
Heiko Schocher621ff132019-12-01 11:23:19 +010090 struct bmp_header *header;
Heiko Schocher0f1130b2019-12-01 11:23:11 +010091 unsigned char *in_logo;
92 int i, j;
93
94 if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
95 return;
96
Heiko Schocher621ff132019-12-01 11:23:19 +010097 header = (struct bmp_header *)bmp_logo_bitmap;
98 in_logo = bmp_logo_bitmap + header->data_offset;
Heiko Schocher0f1130b2019-12-01 11:23:11 +010099
100 /* one 90 degree rotation */
101 if (rotations == 1 || rotations == 2 || rotations == 3)
102 rotate_logo_one(out_logo, in_logo);
103
104 /* second 90 degree rotation */
105 if (rotations == 2 || rotations == 3)
106 rotate_logo_one(in_logo, out_logo);
107
108 /* third 90 degree rotation */
109 if (rotations == 3)
110 rotate_logo_one(out_logo, in_logo);
111
112 /* copy result back to original array */
113 if (rotations == 1 || rotations == 3)
114 for (i = 0; i < BMP_LOGO_WIDTH; i++)
115 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
116 in_logo[i * BMP_LOGO_WIDTH + j] =
117 out_logo[i * BMP_LOGO_WIDTH + j];
118}
119
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100120static void enable_lvds(struct display_info_t const *dev)
121{
122 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
123 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
124 int reg;
125 s32 timeout = 100000;
126
127 /* set PLL5 clock */
128 reg = readl(&ccm->analog_pll_video);
129 reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
130 writel(reg, &ccm->analog_pll_video);
131
132 /* set PLL5 to 232720000Hz */
133 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
134 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
135 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
136 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
137 writel(reg, &ccm->analog_pll_video);
138
139 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
140 &ccm->analog_pll_video_num);
141 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
142 &ccm->analog_pll_video_denom);
143
144 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
145 writel(reg, &ccm->analog_pll_video);
146
147 while (timeout--)
148 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
149 break;
150 if (timeout < 0)
151 printf("Warning: video pll lock timeout!\n");
152
153 reg = readl(&ccm->analog_pll_video);
154 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
155 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
156 writel(reg, &ccm->analog_pll_video);
157
158 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
159 reg = readl(&ccm->cs2cdr);
160 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
161 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
162 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
163 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
164 writel(reg, &ccm->cs2cdr);
165
166 reg = readl(&ccm->cscmr2);
167 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
168 writel(reg, &ccm->cscmr2);
169
170 reg = readl(&ccm->chsccdr);
171 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
172 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
173 writel(reg, &ccm->chsccdr);
174
175 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
176 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
177 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
178 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
179 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
180 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
181 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
182 writel(reg, &iomux->gpr[2]);
183
184 reg = readl(&iomux->gpr[3]);
185 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
186 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
187 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
188 writel(reg, &iomux->gpr[3]);
189}
190
191static void enable_spi_display(struct display_info_t const *dev)
192{
193 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
194 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
195 int reg;
196 s32 timeout = 100000;
197
198#if defined(CONFIG_VIDEO_BMP_LOGO)
199 rotate_logo(3); /* portrait display in landscape mode */
200#endif
201
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100202 reg = readl(&ccm->cs2cdr);
203
204 /* select pll 5 clock */
205 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
206 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
207 writel(reg, &ccm->cs2cdr);
208
209 /* set PLL5 to 197994996Hz */
210 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
211 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
212 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
213 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
214 writel(reg, &ccm->analog_pll_video);
215
216 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
217 &ccm->analog_pll_video_num);
218 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
219 &ccm->analog_pll_video_denom);
220
221 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
222 writel(reg, &ccm->analog_pll_video);
223
224 while (timeout--)
225 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
226 break;
227 if (timeout < 0)
228 printf("Warning: video pll lock timeout!\n");
229
230 reg = readl(&ccm->analog_pll_video);
231 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
232 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
233 writel(reg, &ccm->analog_pll_video);
234
235 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
236 reg = readl(&ccm->cs2cdr);
237 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
238 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
239 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
240 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
241 writel(reg, &ccm->cs2cdr);
242
243 reg = readl(&ccm->cscmr2);
244 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
245 writel(reg, &ccm->cscmr2);
246
247 reg = readl(&ccm->chsccdr);
248 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
249 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
250 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
251 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
252 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
253 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
254 writel(reg, &ccm->chsccdr);
255
256 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
257 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
258 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
259 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
260 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
261 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
262 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
263 writel(reg, &iomux->gpr[2]);
264
265 reg = readl(&iomux->gpr[3]);
266 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
267 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
268 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
269 writel(reg, &iomux->gpr[3]);
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100270}
271
272static void setup_display(void)
273{
274 enable_ipu_clock();
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100275}
276
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100277static void set_gpr_register(void)
278{
279 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
280
281 writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
282 IOMUXC_GPR1_EXC_MON_SLVE |
283 (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
284 IOMUXC_GPR1_ACT_CS0,
285 &iomuxc_regs->gpr[1]);
286 writel(0x0, &iomuxc_regs->gpr[8]);
287 writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
288 IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
289 &iomuxc_regs->gpr[12]);
290}
291
Heiko Schocherccc75952019-12-01 11:23:12 +0100292extern char __bss_start[], __bss_end[];
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100293int board_early_init_f(void)
294{
Heiko Schocher621ff132019-12-01 11:23:19 +0100295 select_ldb_di_clock_source(MXC_PLL5_CLK);
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100296 set_gpr_register();
Heiko Schocherccc75952019-12-01 11:23:12 +0100297
298 /*
299 * clear bss here, so we can use spi driver
300 * before relocation and read Environment
301 * from spi flash.
302 */
303 memset(__bss_start, 0x00, __bss_end - __bss_start);
304
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100305 return 0;
306}
307
Heiko Schocherfc7e3cc2019-12-01 11:23:15 +0100308static void setup_one_led(char *label, int state)
309{
310 struct udevice *dev;
311 int ret;
312
313 ret = led_get_by_label(label, &dev);
314 if (ret == 0)
315 led_set_state(dev, state);
316}
317
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100318static void setup_board_gpio(void)
319{
Heiko Schocherfc7e3cc2019-12-01 11:23:15 +0100320 setup_one_led("led_ena", LEDST_ON);
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100321 /* switch off Status LEDs */
Heiko Schocherfc7e3cc2019-12-01 11:23:15 +0100322 setup_one_led("led_yellow", LEDST_OFF);
323 setup_one_led("led_red", LEDST_OFF);
324 setup_one_led("led_green", LEDST_OFF);
325 setup_one_led("led_blue", LEDST_OFF);
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100326}
327
Heiko Schocherf7cf76f2019-12-01 11:23:23 +0100328#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
329 " rescueReason=%d "
330
331static void aristainetos_run_rescue_command(int reason)
332{
333 char rescue_reason_command[80];
334
335 sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
336 run_command(rescue_reason_command, 0);
337}
338
339static int aristainetos_eeprom(void)
340{
341 struct udevice *dev;
342 int off;
343 int ret;
344 u8 data[0x10];
345 u8 rescue_reason;
346
347 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
348 if (off < 0) {
349 printf("%s: No eeprom0 path offset\n", __func__);
350 return off;
351 }
352
353 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
354 if (ret) {
355 printf("%s: Could not find EEPROM\n", __func__);
356 return ret;
357 }
358
359 ret = i2c_set_chip_offset_len(dev, 2);
360 if (ret)
361 return ret;
362
363 ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
364 if (ret) {
365 printf("%s: Could not read EEPROM\n", __func__);
366 return ret;
367 }
368
369 if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
370 rescue_reason = *(uint8_t *)&data[9];
371 memset(&data[3], 0xff, 7);
372 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
373 printf("\nBooting into Rescue System (EEPROM)\n");
374 aristainetos_run_rescue_command(rescue_reason);
375 run_command("run rescue_load_fit rescueboot", 0);
376 } else if (strncmp((char *)data, "DeF", 3) == 0) {
377 memset(data, 0xff, 3);
378 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
379 printf("\nClear u-boot environment (set back to defaults)\n");
380 run_command("run default_env; saveenv; saveenv", 0);
381 }
382
383 return 0;
384};
385
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100386int board_late_init(void)
387{
388 char *my_bootdelay;
389 char bootmode = 0;
Heiko Schocherfc7e3cc2019-12-01 11:23:15 +0100390 struct gpio_desc *desc;
Heiko Schocher621ff132019-12-01 11:23:19 +0100391 int x, y;
Heiko Schocherfc7e3cc2019-12-01 11:23:15 +0100392 int ret;
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100393
Heiko Schocherfc7e3cc2019-12-01 11:23:15 +0100394 led_default_state();
Heiko Schocher621ff132019-12-01 11:23:19 +0100395 splash_get_pos(&x, &y);
396 bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100397 /*
398 * Check the boot-source. If booting from NOR Flash,
399 * disable bootdelay
400 */
Heiko Schocherfc7e3cc2019-12-01 11:23:15 +0100401 desc = gpio_hog_lookup_name("bootsel0");
402 if (desc)
403 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
404 desc = gpio_hog_lookup_name("bootsel1");
405 if (desc)
406 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
407 desc = gpio_hog_lookup_name("bootsel2");
408 if (desc)
409 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100410
411 if (bootmode == 7) {
412 my_bootdelay = env_get("nor_bootdelay");
413 if (my_bootdelay != NULL)
414 env_set("bootdelay", my_bootdelay);
415 else
416 env_set("bootdelay", "-2");
417 }
418
Heiko Schocherfc7e3cc2019-12-01 11:23:15 +0100419 /* read out some jumper values*/
420 ret = gpio_hog_lookup_name("env_reset", &desc);
421 if (!ret) {
422 if (dm_gpio_get_value(desc)) {
423 printf("\nClear env (set back to defaults)\n");
424 run_command("run default_env; saveenv; saveenv", 0);
425 }
426 }
427 ret = gpio_hog_lookup_name("boot_rescue", &desc);
428 if (!ret) {
429 if (dm_gpio_get_value(desc)) {
430 aristainetos_run_rescue_command(16);
431 run_command("run rescue_xload_boot", 0);
432 }
433 }
434
Heiko Schocherf7cf76f2019-12-01 11:23:23 +0100435 /* eeprom work */
436 aristainetos_eeprom();
437
Heiko Schocherccc75952019-12-01 11:23:12 +0100438 /* set board_type */
439 if (gd->board_type == BOARD_TYPE_4)
440 env_set("board_type", ARI_BT_4);
441 else
442 env_set("board_type", ARI_BT_7);
Heiko Schocher0f1130b2019-12-01 11:23:11 +0100443 return 0;
444}
Heiko Schocher7254d922015-05-18 13:32:31 +0200445
Heiko Schocher7254d922015-05-18 13:32:31 +0200446int dram_init(void)
Heiko Schocher2f6bb0a2014-10-30 13:14:03 +0100447{
Fabio Estevam84c51682016-07-23 13:23:39 -0300448 gd->ram_size = imx_ddr_size();
Heiko Schocher2f6bb0a2014-10-30 13:14:03 +0100449
Heiko Schocher7254d922015-05-18 13:32:31 +0200450 return 0;
Heiko Schochere379c032014-07-18 06:07:22 +0200451}
452
Heiko Schochere379c032014-07-18 06:07:22 +0200453struct display_info_t const displays[] = {
454 {
455 .bus = -1,
456 .addr = 0,
457 .pixfmt = IPU_PIX_FMT_RGB24,
458 .detect = NULL,
459 .enable = enable_lvds,
460 .mode = {
461 .name = "lb07wv8",
462 .refresh = 60,
463 .xres = 800,
464 .yres = 480,
Heiko Schocherd0d005b2015-08-11 08:09:44 +0200465 .pixclock = 30066,
Heiko Schochere379c032014-07-18 06:07:22 +0200466 .left_margin = 88,
467 .right_margin = 88,
Heiko Schocherd0d005b2015-08-11 08:09:44 +0200468 .upper_margin = 20,
469 .lower_margin = 20,
Heiko Schocherb4b39a72015-01-20 10:06:18 +0100470 .hsync_len = 80,
Heiko Schocherd0d005b2015-08-11 08:09:44 +0200471 .vsync_len = 5,
472 .sync = FB_SYNC_EXT,
Heiko Schochere379c032014-07-18 06:07:22 +0200473 .vmode = FB_VMODE_NONINTERLACED
474 }
475 }
Heiko Schocher96270842015-08-24 11:36:40 +0200476#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
Heiko Schocher7254d922015-05-18 13:32:31 +0200477 , {
478 .bus = -1,
479 .addr = 0,
480 .pixfmt = IPU_PIX_FMT_RGB24,
481 .detect = NULL,
482 .enable = enable_spi_display,
483 .mode = {
484 .name = "lg4573",
Heiko Schocherd0d005b2015-08-11 08:09:44 +0200485 .refresh = 57,
Heiko Schocher7254d922015-05-18 13:32:31 +0200486 .xres = 480,
487 .yres = 800,
488 .pixclock = 37037,
489 .left_margin = 59,
490 .right_margin = 10,
491 .upper_margin = 15,
492 .lower_margin = 15,
493 .hsync_len = 10,
494 .vsync_len = 15,
495 .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
496 FB_SYNC_VERT_HIGH_ACT,
497 .vmode = FB_VMODE_NONINTERLACED
498 }
499 }
500#endif
Heiko Schochere379c032014-07-18 06:07:22 +0200501};
502size_t display_count = ARRAY_SIZE(displays);
503
Heiko Schochere379c032014-07-18 06:07:22 +0200504iomux_v3_cfg_t nfc_pads[] = {
505 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
506 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
507 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
508 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
509 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
Heiko Schochere379c032014-07-18 06:07:22 +0200510 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
511 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
512 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
513 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
514 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
515 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
516 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
517 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
518 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
519 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
520 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
521};
522
523static void setup_gpmi_nand(void)
524{
525 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
526
527 /* config gpmi nand iomux */
528 imx_iomux_v3_setup_multiple_pads(nfc_pads,
529 ARRAY_SIZE(nfc_pads));
530
Heiko Schocher7254d922015-05-18 13:32:31 +0200531 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
532 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
533
Heiko Schochere379c032014-07-18 06:07:22 +0200534 /* config gpmi and bch clock to 100 MHz */
535 clrsetbits_le32(&mxc_ccm->cs2cdr,
536 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
537 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
538 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
539 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
540 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
541 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
542
Heiko Schocher7254d922015-05-18 13:32:31 +0200543 /* enable ENFC_CLK_ROOT clock */
544 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
545
Heiko Schochere379c032014-07-18 06:07:22 +0200546 /* enable gpmi and bch clock gating */
547 setbits_le32(&mxc_ccm->CCGR4,
548 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
549 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
550 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
551 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
552 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
553
554 /* enable apbh clock gating */
555 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
556}
557
558int board_init(void)
559{
560 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
561
562 /* address of boot parameters */
563 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
564
Heiko Schocher7254d922015-05-18 13:32:31 +0200565 setup_board_gpio();
Heiko Schochere379c032014-07-18 06:07:22 +0200566 setup_gpmi_nand();
Heiko Schocher621ff132019-12-01 11:23:19 +0100567 setup_display();
Heiko Schochere379c032014-07-18 06:07:22 +0200568
569 /* GPIO_1 for USB_OTG_ID */
Heiko Schocher7254d922015-05-18 13:32:31 +0200570 clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
Heiko Schochere379c032014-07-18 06:07:22 +0200571 return 0;
572}
573
Heiko Schocherccc75952019-12-01 11:23:12 +0100574int board_fit_config_name_match(const char *name)
575{
576 if (gd->board_type == BOARD_TYPE_4 &&
577 strchr(name, 0x34))
578 return 0;
579
580 if (gd->board_type == BOARD_TYPE_7 &&
581 strchr(name, 0x37))
582 return 0;
583
584 return -1;
585}
586
587static void do_board_detect(void)
588{
589 int ret;
590 char s[30];
591
592 /* default use board type 7 */
593 gd->board_type = BOARD_TYPE_7;
594 if (env_init())
595 return;
596
597 ret = env_get_f("panel", s, sizeof(s));
598 if (ret < 0)
599 return;
600
601 if (!strncmp("lg4573", s, 6))
602 gd->board_type = BOARD_TYPE_4;
603}
604
605#ifdef CONFIG_DTB_RESELECT
606int embedded_dtb_select(void)
607{
608 int rescan;
609
610 do_board_detect();
611 fdtdec_resetup(&rescan);
612
Heiko Schochere379c032014-07-18 06:07:22 +0200613 return 0;
614}
615#endif