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York Sun9a17eb52013-11-18 10:29:32 -08001/*
2 * Common internal memory map for some Freescale SoCs
3 *
York Sun34e026f2014-03-27 17:54:47 -07004 * Copyright 2013-2014 Freescale Semiconductor, Inc.
York Sun9a17eb52013-11-18 10:29:32 -08005 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __FSL_IMMAP_H
10#define __FSL_IMMAP_H
11/*
12 * DDR memory controller registers
13 * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
14 */
15struct ccsr_ddr {
16 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
17 u8 res_04[4];
18 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
19 u8 res_0c[4];
20 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
21 u8 res_14[4];
22 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
23 u8 res_1c[100];
24 u32 cs0_config; /* Chip Select Configuration */
25 u32 cs1_config; /* Chip Select Configuration */
26 u32 cs2_config; /* Chip Select Configuration */
27 u32 cs3_config; /* Chip Select Configuration */
28 u8 res_90[48];
29 u32 cs0_config_2; /* Chip Select Configuration 2 */
30 u32 cs1_config_2; /* Chip Select Configuration 2 */
31 u32 cs2_config_2; /* Chip Select Configuration 2 */
32 u32 cs3_config_2; /* Chip Select Configuration 2 */
33 u8 res_d0[48];
34 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
35 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
36 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
37 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
38 u32 sdram_cfg; /* SDRAM Control Configuration */
39 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
40 u32 sdram_mode; /* SDRAM Mode Configuration */
41 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
42 u32 sdram_md_cntl; /* SDRAM Mode Control */
43 u32 sdram_interval; /* SDRAM Interval Configuration */
44 u32 sdram_data_init; /* SDRAM Data initialization */
45 u8 res_12c[4];
46 u32 sdram_clk_cntl; /* SDRAM Clock Control */
47 u8 res_134[20];
48 u32 init_addr; /* training init addr */
49 u32 init_ext_addr; /* training init extended addr */
50 u8 res_150[16];
51 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
52 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
York Sun34e026f2014-03-27 17:54:47 -070053 u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */
54 u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */
York Sun9a17eb52013-11-18 10:29:32 -080055 u32 ddr_zq_cntl; /* ZQ calibration control*/
56 u32 ddr_wrlvl_cntl; /* write leveling control*/
57 u8 reg_178[4];
58 u32 ddr_sr_cntr; /* self refresh counter */
59 u32 ddr_sdram_rcw_1; /* Control Words 1 */
60 u32 ddr_sdram_rcw_2; /* Control Words 2 */
61 u8 reg_188[8];
62 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
63 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
York Sun34e026f2014-03-27 17:54:47 -070064 u8 res_198[0x1a0-0x198];
65 u32 ddr_sdram_rcw_3;
66 u32 ddr_sdram_rcw_4;
67 u32 ddr_sdram_rcw_5;
68 u32 ddr_sdram_rcw_6;
69 u8 res_1b0[0x200-0x1b0];
York Sun9a17eb52013-11-18 10:29:32 -080070 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
71 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
72 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
73 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
74 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
75 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
York Sun34e026f2014-03-27 17:54:47 -070076 u8 res_218[0x220-0x218];
77 u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */
78 u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */
79 u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */
80 u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */
81 u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */
82 u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */
83 u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */
84 u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */
85 u8 res_240[0x250-0x240];
86 u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */
87 u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
88 u8 res_258[0x260-0x258];
89 u32 sdram_cfg_3;
90 u8 res_264[0x2a0-0x264];
91 u32 deskew_cntl;
92 u8 res_2a4[0x400-0x2a4];
93 u32 dq_map_0;
94 u32 dq_map_1;
95 u32 dq_map_2;
96 u32 dq_map_3;
97 u8 res_410[0xb20-0x410];
York Sun9a17eb52013-11-18 10:29:32 -080098 u32 ddr_dsr1; /* Debug Status 1 */
99 u32 ddr_dsr2; /* Debug Status 2 */
100 u32 ddr_cdr1; /* Control Driver 1 */
101 u32 ddr_cdr2; /* Control Driver 2 */
102 u8 res_b30[200];
103 u32 ip_rev1; /* IP Block Revision 1 */
104 u32 ip_rev2; /* IP Block Revision 2 */
105 u32 eor; /* Enhanced Optimization Register */
106 u8 res_c04[252];
107 u32 mtcr; /* Memory Test Control Register */
108 u8 res_d04[28];
109 u32 mtp1; /* Memory Test Pattern 1 */
110 u32 mtp2; /* Memory Test Pattern 2 */
111 u32 mtp3; /* Memory Test Pattern 3 */
112 u32 mtp4; /* Memory Test Pattern 4 */
113 u32 mtp5; /* Memory Test Pattern 5 */
114 u32 mtp6; /* Memory Test Pattern 6 */
115 u32 mtp7; /* Memory Test Pattern 7 */
116 u32 mtp8; /* Memory Test Pattern 8 */
117 u32 mtp9; /* Memory Test Pattern 9 */
118 u32 mtp10; /* Memory Test Pattern 10 */
119 u8 res_d48[184];
120 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
121 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
122 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
123 u8 res_e0c[20];
124 u32 capture_data_hi; /* Data Path Read Capture High */
125 u32 capture_data_lo; /* Data Path Read Capture Low */
126 u32 capture_ecc; /* Data Path Read Capture ECC */
127 u8 res_e2c[20];
128 u32 err_detect; /* Error Detect */
129 u32 err_disable; /* Error Disable */
130 u32 err_int_en;
131 u32 capture_attributes; /* Error Attrs Capture */
132 u32 capture_address; /* Error Addr Capture */
133 u32 capture_ext_address; /* Error Extended Addr Capture */
134 u32 err_sbe; /* Single-Bit ECC Error Management */
135 u8 res_e5c[164];
136 u32 debug[32]; /* debug_1 to debug_32 */
137 u8 res_f80[128];
138};
139#endif /* __FSL_IMMAP_H */