blob: 9c05c2f17280a8282b3bda7604b7f6effad82470 [file] [log] [blame]
Joe Hamman11c45eb2007-12-13 06:45:08 -06001/*
2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 *
5 * Copyright 2004, 2007 Freescale Semiconductor.
6 *
7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <pci.h>
30#include <asm/processor.h>
31#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050032#include <asm/fsl_pci.h>
Kumar Gala33b90792008-08-26 23:15:28 -050033#include <asm/fsl_ddr_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060034#include <spd_sdram.h>
Joe Hamman11c45eb2007-12-13 06:45:08 -060035#include <miiphy.h>
36#include <libfdt.h>
37#include <fdt_support.h>
38
Joe Hamman11c45eb2007-12-13 06:45:08 -060039DECLARE_GLOBAL_DATA_PTR;
40
Joe Hamman11c45eb2007-12-13 06:45:08 -060041void local_bus_init(void);
42void sdram_init(void);
43long int fixed_sdram (void);
44
45int board_early_init_f (void)
46{
47 return 0;
48}
49
50int checkboard (void)
51{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
53 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
54 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
Joe Hamman11c45eb2007-12-13 06:45:08 -060055
56 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
Jean-Christophe PLAGNIOL-VILLARD347b7932008-02-17 22:56:17 +010057 (*rev) >> 4);
Joe Hamman11c45eb2007-12-13 06:45:08 -060058
59 /*
60 * Initialize local bus.
61 */
62 local_bus_init ();
63
64 /*
Joe Hamman11c45eb2007-12-13 06:45:08 -060065 * Hack TSEC 3 and 4 IO voltages.
66 */
67 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
68
69 ecm->eedr = 0xffffffff; /* clear ecm errors */
70 ecm->eeer = 0xffffffff; /* enable ecm errors */
71 return 0;
72}
73
Becky Bruce9973e3c2008-06-09 16:03:40 -050074phys_size_t
Joe Hamman11c45eb2007-12-13 06:45:08 -060075initdram(int board_type)
76{
77 long dram_size = 0;
78
79 puts("Initializing\n");
80
81#if defined(CONFIG_DDR_DLL)
82 {
83 /*
84 * Work around to stabilize DDR DLL MSYNC_IN.
85 * Errata DDR9 seems to have been fixed.
86 * This is now the workaround for Errata DDR11:
87 * Override DLL = 1, Course Adj = 1, Tap Select = 0
88 */
89
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Joe Hamman11c45eb2007-12-13 06:45:08 -060091
92 gur->ddrdllcr = 0x81000000;
93 asm("sync;isync;msync");
94 udelay(200);
95 }
96#endif
97
98#if defined(CONFIG_SPD_EEPROM)
Kumar Gala33b90792008-08-26 23:15:28 -050099 dram_size = fsl_ddr_sdram();
100 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
101 dram_size *= 0x100000;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600102#else
103 dram_size = fixed_sdram ();
104#endif
105
Joe Hamman11c45eb2007-12-13 06:45:08 -0600106 /*
107 * SDRAM Initialization
108 */
109 sdram_init();
110
111 puts(" DDR: ");
112 return dram_size;
113}
114
115/*
116 * Initialize Local Bus
117 */
118void
119local_bus_init(void)
120{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
122 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600123
124 uint clkdiv;
125 uint lbc_hz;
126 sys_info_t sysinfo;
127
128 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800129 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600130 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
131
132 gur->lbiuiplldcr1 = 0x00078080;
133 if (clkdiv == 16) {
134 gur->lbiuiplldcr0 = 0x7c0f1bf0;
135 } else if (clkdiv == 8) {
136 gur->lbiuiplldcr0 = 0x6c0f1bf0;
137 } else if (clkdiv == 4) {
138 gur->lbiuiplldcr0 = 0x5c0f1bf0;
139 }
140
141 lbc->lcrr |= 0x00030000;
142
143 asm("sync;isync;msync");
144
145 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
146 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
147}
148
149/*
150 * Initialize SDRAM memory on the Local Bus.
151 */
152void
153sdram_init(void)
154{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600156
157 uint idx;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
159 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600160 uint lsdmr_common;
161
162 puts(" SDRAM: ");
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
Joe Hamman11c45eb2007-12-13 06:45:08 -0600165
166 /*
167 * Setup SDRAM Base and Option Registers
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 lbc->or3 = CONFIG_SYS_OR3_PRELIM;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600170 asm("msync");
171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 lbc->br3 = CONFIG_SYS_BR3_PRELIM;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600173 asm("msync");
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600176 asm("msync");
177
178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
180 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600181 asm("msync");
182
183 /*
184 * MPC8548 uses "new" 15-16 style addressing.
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500187 lsdmr_common |= LSDMR_BSMA1516;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600188
189 /*
190 * Issue PRECHARGE ALL command.
191 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500192 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600193 asm("sync;msync");
194 *sdram_addr = 0xff;
195 ppcDcbf((unsigned long) sdram_addr);
196 udelay(100);
197
198 /*
199 * Issue 8 AUTO REFRESH commands.
200 */
201 for (idx = 0; idx < 8; idx++) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500202 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600203 asm("sync;msync");
204 *sdram_addr = 0xff;
205 ppcDcbf((unsigned long) sdram_addr);
206 udelay(100);
207 }
208
209 /*
210 * Issue 8 MODE-set command.
211 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500212 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600213 asm("sync;msync");
214 *sdram_addr = 0xff;
215 ppcDcbf((unsigned long) sdram_addr);
216 udelay(100);
217
218 /*
219 * Issue NORMAL OP command.
220 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500221 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600222 asm("sync;msync");
223 *sdram_addr = 0xff;
224 ppcDcbf((unsigned long) sdram_addr);
225 udelay(200); /* Overkill. Must wait > 200 bus cycles */
226
227#endif /* enable SDRAM init */
228}
229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#if defined(CONFIG_SYS_DRAM_TEST)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600231int
232testdram(void)
233{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
235 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600236 uint *p;
237
238 printf("Testing DRAM from 0x%08x to 0x%08x\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239 CONFIG_SYS_MEMTEST_START,
240 CONFIG_SYS_MEMTEST_END);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600241
242 printf("DRAM test phase 1:\n");
243 for (p = pstart; p < pend; p++)
244 *p = 0xaaaaaaaa;
245
246 for (p = pstart; p < pend; p++) {
247 if (*p != 0xaaaaaaaa) {
248 printf ("DRAM test fails at: %08x\n", (uint) p);
249 return 1;
250 }
251 }
252
253 printf("DRAM test phase 2:\n");
254 for (p = pstart; p < pend; p++)
255 *p = 0x55555555;
256
257 for (p = pstart; p < pend; p++) {
258 if (*p != 0x55555555) {
259 printf ("DRAM test fails at: %08x\n", (uint) p);
260 return 1;
261 }
262 }
263
264 printf("DRAM test passed.\n");
265 return 0;
266}
267#endif
268
269#if !defined(CONFIG_SPD_EEPROM)
270/*************************************************************************
271 * fixed_sdram init -- doesn't use serial presence detect.
272 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
273 ************************************************************************/
274long int fixed_sdram (void)
275{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
Joe Hamman11c45eb2007-12-13 06:45:08 -0600277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600279
280 ddr->cs0_bnds = 0x0000007f;
281 ddr->cs1_bnds = 0x008000ff;
282 ddr->cs2_bnds = 0x00000000;
283 ddr->cs3_bnds = 0x00000000;
284 ddr->cs0_config = 0x80010101;
285 ddr->cs1_config = 0x80010101;
286 ddr->cs2_config = 0x00000000;
287 ddr->cs3_config = 0x00000000;
Kumar Gala45239cf2008-04-29 10:27:08 -0500288 ddr->timing_cfg_3 = 0x00000000;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600289 ddr->timing_cfg_0 = 0x00220802;
290 ddr->timing_cfg_1 = 0x38377322;
291 ddr->timing_cfg_2 = 0x0fa044C7;
292 ddr->sdram_cfg = 0x4300C000;
293 ddr->sdram_cfg_2 = 0x24401000;
294 ddr->sdram_mode = 0x23C00542;
295 ddr->sdram_mode_2 = 0x00000000;
296 ddr->sdram_interval = 0x05080100;
297 ddr->sdram_md_cntl = 0x00000000;
298 ddr->sdram_data_init = 0x00000000;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200299 ddr->sdram_clk_cntl = 0x03800000;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600300 asm("sync;isync;msync");
301 udelay(500);
302
303 #if defined (CONFIG_DDR_ECC)
304 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600306 #else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600308 #endif
309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600311}
312#endif
313
314#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
315/* For some reason the Tundra PCI bridge shows up on itself as a
316 * different device. Work around that by refusing to configure it.
317 */
318void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
319
320static struct pci_config_table pci_sbc8548_config_table[] = {
321 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
322 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
323 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
324 mpc85xx_config_via_usbide, {0,0,0}},
325 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
326 mpc85xx_config_via_usb, {0,0,0}},
327 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
328 mpc85xx_config_via_usb2, {0,0,0}},
329 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
330 mpc85xx_config_via_power, {0,0,0}},
331 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
332 mpc85xx_config_via_ac97, {0,0,0}},
333 {},
334};
335
336static struct pci_controller pci1_hose = {
337 config_table: pci_sbc8548_config_table};
338#endif /* CONFIG_PCI */
339
340#ifdef CONFIG_PCI2
341static struct pci_controller pci2_hose;
342#endif /* CONFIG_PCI2 */
343
344#ifdef CONFIG_PCIE1
345static struct pci_controller pcie1_hose;
346#endif /* CONFIG_PCIE1 */
347
348int first_free_busno=0;
349
350void
351pci_init_board(void)
352{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600354
355#ifdef CONFIG_PCI1
356{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600358 struct pci_controller *hose = &pci1_hose;
359 struct pci_config_table *table;
Kumar Gala2dba0de2008-10-21 08:28:33 -0500360 struct pci_region *r = hose->regions;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600361
362 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
363 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
364 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
365
366 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
367
368 uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
369
370 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
371 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
372 (pci_32) ? 32 : 64,
373 (pci_speed == 33333000) ? "33" :
374 (pci_speed == 66666000) ? "66" : "unknown",
375 pci_clk_sel ? "sync" : "async",
376 pci_agent ? "agent" : "host",
377 pci_arb ? "arbiter" : "external-arbiter"
378 );
379
380
381 /* inbound */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500382 r += fsl_pci_setup_inbound_windows(r);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600383
384 /* outbound memory */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500385 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386 CONFIG_SYS_PCI1_MEM_BASE,
387 CONFIG_SYS_PCI1_MEM_PHYS,
388 CONFIG_SYS_PCI1_MEM_SIZE,
Joe Hamman11c45eb2007-12-13 06:45:08 -0600389 PCI_REGION_MEM);
390
391 /* outbound io */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500392 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393 CONFIG_SYS_PCI1_IO_BASE,
394 CONFIG_SYS_PCI1_IO_PHYS,
395 CONFIG_SYS_PCI1_IO_SIZE,
Joe Hamman11c45eb2007-12-13 06:45:08 -0600396 PCI_REGION_IO);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500397 hose->region_count = r - hose->regions;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600398
399 /* relocate config table pointers */
400 hose->config_table = \
401 (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
402 for (table = hose->config_table; table && table->vendor; table++)
403 table->config_device += gd->reloc_off;
404
405 hose->first_busno=first_free_busno;
406 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
407
408 fsl_pci_init(hose);
409 first_free_busno=hose->last_busno+1;
410 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
411#ifdef CONFIG_PCIX_CHECK
Peter Tyser9427ccd2008-12-01 13:47:12 -0600412 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
Joe Hamman11c45eb2007-12-13 06:45:08 -0600413 /* PCI-X init */
414 if (CONFIG_SYS_CLK_FREQ < 66000000)
415 printf("PCI-X will only work at 66 MHz\n");
416
417 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
418 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
419 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
420 }
421#endif
422 } else {
423 printf (" PCI: disabled\n");
424 }
425}
426#else
427 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
428#endif
429
430#ifdef CONFIG_PCI2
431{
432 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
433 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
434 if (pci_dual) {
435 printf (" PCI2: 32 bit, 66 MHz, %s\n",
436 pci2_clk_sel ? "sync" : "async");
437 } else {
438 printf (" PCI2: disabled\n");
439 }
440}
441#else
442 gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
443#endif /* CONFIG_PCI2 */
444
445#ifdef CONFIG_PCIE1
446{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600448 struct pci_controller *hose = &pcie1_hose;
449 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500450 struct pci_region *r = hose->regions;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600451
452 int pcie_configured = io_sel >= 1;
453
454 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
455 printf ("\n PCIE connected to slot as %s (base address %x)",
456 pcie_ep ? "End Point" : "Root Complex",
457 (uint)pci);
458
459 if (pci->pme_msg_det) {
460 pci->pme_msg_det = 0xffffffff;
461 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
462 }
463 printf ("\n");
464
465 /* inbound */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500466 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467 CONFIG_SYS_PCI_MEMORY_BUS,
468 CONFIG_SYS_PCI_MEMORY_PHYS,
469 CONFIG_SYS_PCI_MEMORY_SIZE,
Kumar Galaff4e66e2009-02-06 09:49:31 -0600470 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600471
472 /* outbound memory */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500473 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474 CONFIG_SYS_PCIE1_MEM_BASE,
475 CONFIG_SYS_PCIE1_MEM_PHYS,
476 CONFIG_SYS_PCIE1_MEM_SIZE,
Joe Hamman11c45eb2007-12-13 06:45:08 -0600477 PCI_REGION_MEM);
478
479 /* outbound io */
Kumar Gala2dba0de2008-10-21 08:28:33 -0500480 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481 CONFIG_SYS_PCIE1_IO_BASE,
482 CONFIG_SYS_PCIE1_IO_PHYS,
483 CONFIG_SYS_PCIE1_IO_SIZE,
Joe Hamman11c45eb2007-12-13 06:45:08 -0600484 PCI_REGION_IO);
485
Kumar Gala2dba0de2008-10-21 08:28:33 -0500486 hose->region_count = r - hose->regions;
Joe Hamman11c45eb2007-12-13 06:45:08 -0600487
488 hose->first_busno=first_free_busno;
489 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
490
491 fsl_pci_init(hose);
492 printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
493
494 first_free_busno=hose->last_busno+1;
495
496 } else {
497 printf (" PCIE: disabled\n");
498 }
499 }
500#else
501 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
502#endif
503
504}
505
506int last_stage_init(void)
507{
508 return 0;
509}
510
511#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500512void ft_board_setup(void *blob, bd_t *bd)
Joe Hamman11c45eb2007-12-13 06:45:08 -0600513{
514 ft_cpu_setup(blob, bd);
Kumar Gala2dba0de2008-10-21 08:28:33 -0500515#ifdef CONFIG_PCI1
516 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
517#endif
518#ifdef CONFIG_PCIE1
519 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
Joe Hamman11c45eb2007-12-13 06:45:08 -0600520#endif
521}
522#endif