blob: 17d3efdf146968b9ea60a47ec10045e49be6a4d8 [file] [log] [blame]
Beniamino Galvanibfcef282016-05-08 08:30:16 +02001/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
Heiner Kallweita3b02a12017-04-12 20:28:36 +020043#include "meson-gx.dtsi"
Beniamino Galvanidd838402016-08-16 11:49:48 +020044#include <dt-bindings/gpio/meson-gxbb-gpio.h>
45#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
Heiner Kallweita3b02a12017-04-12 20:28:36 +020046#include <dt-bindings/clock/gxbb-clkc.h>
47#include <dt-bindings/clock/gxbb-aoclkc.h>
48#include <dt-bindings/reset/gxbb-aoclkc.h>
Beniamino Galvanibfcef282016-05-08 08:30:16 +020049
50/ {
51 compatible = "amlogic,meson-gxbb";
Beniamino Galvanibfcef282016-05-08 08:30:16 +020052
53 soc {
Heiner Kallweita3b02a12017-04-12 20:28:36 +020054 usb0_phy: phy@c0000000 {
55 compatible = "amlogic,meson-gxbb-usb2-phy";
56 #phy-cells = <0>;
57 reg = <0x0 0xc0000000 0x0 0x20>;
58 resets = <&reset RESET_USB_OTG>;
59 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
60 clock-names = "usb_general", "usb";
61 status = "disabled";
62 };
63
64 usb1_phy: phy@c0000020 {
65 compatible = "amlogic,meson-gxbb-usb2-phy";
66 #phy-cells = <0>;
67 reg = <0x0 0xc0000020 0x0 0x20>;
68 resets = <&reset RESET_USB_OTG>;
69 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
70 clock-names = "usb_general", "usb";
71 status = "disabled";
72 };
73
74 usb0: usb@c9000000 {
75 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
76 reg = <0x0 0xc9000000 0x0 0x40000>;
77 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
79 clock-names = "otg";
80 phys = <&usb0_phy>;
81 phy-names = "usb2-phy";
82 dr_mode = "host";
83 status = "disabled";
84 };
85
86 usb1: usb@c9100000 {
87 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
88 reg = <0x0 0xc9100000 0x0 0x40000>;
89 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
91 clock-names = "otg";
92 phys = <&usb1_phy>;
93 phy-names = "usb2-phy";
94 dr_mode = "host";
95 status = "disabled";
96 };
97 };
98};
99
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200100&aobus {
101 pinctrl_aobus: pinctrl@14 {
102 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200103 #address-cells = <2>;
104 #size-cells = <2>;
105 ranges;
106
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200107 gpio_ao: bank@14 {
108 reg = <0x0 0x00014 0x0 0x8>,
109 <0x0 0x0002c 0x0 0x4>,
110 <0x0 0x00024 0x0 0x8>;
111 reg-names = "mux", "pull", "gpio";
112 gpio-controller;
113 #gpio-cells = <2>;
Beniamino Galvani4a63a752017-07-10 00:30:03 +0200114 gpio-ranges = <&pinctrl_aobus 0 0 14>;
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200115 };
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200116
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200117 uart_ao_a_pins: uart_ao_a {
118 mux {
119 groups = "uart_tx_ao_a", "uart_rx_ao_a";
120 function = "uart_ao";
Beniamino Galvanidd838402016-08-16 11:49:48 +0200121 };
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200122 };
123
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200124 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
125 mux {
126 groups = "uart_cts_ao_a",
127 "uart_rts_ao_a";
128 function = "uart_ao";
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200129 };
130 };
131
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200132 uart_ao_b_pins: uart_ao_b {
133 mux {
134 groups = "uart_tx_ao_b", "uart_rx_ao_b";
135 function = "uart_ao_b";
Beniamino Galvanidd838402016-08-16 11:49:48 +0200136 };
137 };
138
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200139 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
140 mux {
141 groups = "uart_cts_ao_b",
142 "uart_rts_ao_b";
143 function = "uart_ao_b";
Beniamino Galvanidd838402016-08-16 11:49:48 +0200144 };
145 };
146
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200147 remote_input_ao_pins: remote_input_ao {
148 mux {
149 groups = "remote_input_ao";
150 function = "remote_input_ao";
151 };
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200152 };
Beniamino Galvanidd838402016-08-16 11:49:48 +0200153
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200154 i2c_ao_pins: i2c_ao {
155 mux {
156 groups = "i2c_sck_ao",
157 "i2c_sda_ao";
158 function = "i2c_ao";
159 };
160 };
161
162 pwm_ao_a_3_pins: pwm_ao_a_3 {
163 mux {
164 groups = "pwm_ao_a_3";
165 function = "pwm_ao_a_3";
166 };
167 };
168
169 pwm_ao_a_6_pins: pwm_ao_a_6 {
170 mux {
171 groups = "pwm_ao_a_6";
172 function = "pwm_ao_a_6";
173 };
174 };
175
176 pwm_ao_a_12_pins: pwm_ao_a_12 {
177 mux {
178 groups = "pwm_ao_a_12";
179 function = "pwm_ao_a_12";
180 };
181 };
182
183 pwm_ao_b_pins: pwm_ao_b {
184 mux {
185 groups = "pwm_ao_b";
186 function = "pwm_ao_b";
187 };
Beniamino Galvanidd838402016-08-16 11:49:48 +0200188 };
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200189
Beniamino Galvani4a63a752017-07-10 00:30:03 +0200190 i2s_am_clk_pins: i2s_am_clk {
191 mux {
192 groups = "i2s_am_clk";
193 function = "i2s_out_ao";
194 };
195 };
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200196
Beniamino Galvani4a63a752017-07-10 00:30:03 +0200197 i2s_out_ao_clk_pins: i2s_out_ao_clk {
198 mux {
199 groups = "i2s_out_ao_clk";
200 function = "i2s_out_ao";
201 };
202 };
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200203
Beniamino Galvani4a63a752017-07-10 00:30:03 +0200204 i2s_out_lr_clk_pins: i2s_out_lr_clk {
205 mux {
206 groups = "i2s_out_lr_clk";
207 function = "i2s_out_ao";
208 };
209 };
210
211 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
212 mux {
213 groups = "i2s_out_ch01_ao";
214 function = "i2s_out_ao";
215 };
216 };
217
218 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
219 mux {
220 groups = "i2s_out_ch23_ao";
221 function = "i2s_out_ao";
222 };
223 };
224
225 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
226 mux {
227 groups = "i2s_out_ch45_ao";
228 function = "i2s_out_ao";
229 };
230 };
231
232 spdif_out_ao_6_pins: spdif_out_ao_6 {
233 mux {
234 groups = "spdif_out_ao_6";
235 function = "spdif_out_ao";
236 };
237 };
238
239 spdif_out_ao_13_pins: spdif_out_ao_13 {
240 mux {
241 groups = "spdif_out_ao_13";
242 function = "spdif_out_ao";
243 };
244 };
Neil Armstrong48622152017-10-12 15:50:30 +0200245
246 ao_cec_pins: ao_cec {
247 mux {
248 groups = "ao_cec";
249 function = "cec_ao";
250 };
251 };
252
253 ee_cec_pins: ee_cec {
254 mux {
255 groups = "ee_cec";
256 function = "cec_ao";
257 };
258 };
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200259 };
260};
261
Neil Armstrong48622152017-10-12 15:50:30 +0200262&apb {
263 mali: gpu@c0000 {
264 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
265 reg = <0x0 0xc0000 0x0 0x40000>;
266 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "gp", "gpmmu", "pp", "pmu",
277 "pp0", "ppmmu0", "pp1", "ppmmu1",
278 "pp2", "ppmmu2";
279 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
280 clock-names = "bus", "core";
281
282 /*
283 * Mali clocking is provided by two identical clock paths
284 * MALI_0 and MALI_1 muxed to a single clock by a glitch
285 * free mux to safely change frequency while running.
286 */
287 assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
288 <&clkc CLKID_MALI_0>,
289 <&clkc CLKID_MALI>; /* Glitch free mux */
290 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
291 <0>, /* Do Nothing */
292 <&clkc CLKID_MALI_0>;
293 assigned-clock-rates = <0>, /* Do Nothing */
294 <666666666>,
295 <0>; /* Do Nothing */
296 };
297};
298
299&cbus {
300 spifc: spi@8c80 {
301 compatible = "amlogic,meson-gxbb-spifc";
302 reg = <0x0 0x08c80 0x0 0x80>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 clocks = <&clkc CLKID_SPI>;
306 status = "disabled";
307 };
308};
309
310&ethmac {
311 clocks = <&clkc CLKID_ETH>,
312 <&clkc CLKID_FCLK_DIV2>,
313 <&clkc CLKID_MPLL2>;
314 clock-names = "stmmaceth", "clkin0", "clkin1";
315};
316
317&hdmi_tx {
318 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
319 resets = <&reset RESET_HDMITX_CAPB3>,
320 <&reset RESET_HDMI_SYSTEM_RESET>,
321 <&reset RESET_HDMI_TX>;
322 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
323 clocks = <&clkc CLKID_HDMI_PCLK>,
324 <&clkc CLKID_CLK81>,
325 <&clkc CLKID_GCLK_VENCI_INT0>;
326 clock-names = "isfr", "iahb", "venci";
327};
328
329&hiubus {
330 clkc: clock-controller@0 {
331 compatible = "amlogic,gxbb-clkc";
332 #clock-cells = <1>;
333 reg = <0x0 0x0 0x0 0x3db>;
334 };
335};
336
337&hwrng {
338 clocks = <&clkc CLKID_RNG0>;
339 clock-names = "core";
340};
341
342&i2c_A {
343 clocks = <&clkc CLKID_I2C>;
344};
345
346&i2c_AO {
347 clocks = <&clkc CLKID_AO_I2C>;
348};
349
350&i2c_B {
351 clocks = <&clkc CLKID_I2C>;
352};
353
354&i2c_C {
355 clocks = <&clkc CLKID_I2C>;
356};
357
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200358&periphs {
359 pinctrl_periphs: pinctrl@4b0 {
360 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
361 #address-cells = <2>;
362 #size-cells = <2>;
363 ranges;
364
365 gpio: bank@4b0 {
366 reg = <0x0 0x004b0 0x0 0x28>,
367 <0x0 0x004e8 0x0 0x14>,
Neil Armstrong48622152017-10-12 15:50:30 +0200368 <0x0 0x00520 0x0 0x14>,
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200369 <0x0 0x00430 0x0 0x40>;
370 reg-names = "mux", "pull", "pull-enable", "gpio";
371 gpio-controller;
372 #gpio-cells = <2>;
Beniamino Galvani4a63a752017-07-10 00:30:03 +0200373 gpio-ranges = <&pinctrl_periphs 0 14 120>;
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200374 };
375
376 emmc_pins: emmc {
377 mux {
378 groups = "emmc_nand_d07",
379 "emmc_cmd",
380 "emmc_clk",
381 "emmc_ds";
382 function = "emmc";
383 };
384 };
385
386 nor_pins: nor {
387 mux {
388 groups = "nor_d",
389 "nor_q",
390 "nor_c",
391 "nor_cs";
392 function = "nor";
393 };
394 };
395
Neil Armstrong48622152017-10-12 15:50:30 +0200396 spi_pins: spi {
397 mux {
398 groups = "spi_miso",
399 "spi_mosi",
400 "spi_sclk";
401 function = "spi";
402 };
403 };
404
405 spi_ss0_pins: spi-ss0 {
406 mux {
407 groups = "spi_ss0";
408 function = "spi";
409 };
410 };
411
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200412 sdcard_pins: sdcard {
413 mux {
414 groups = "sdcard_d0",
415 "sdcard_d1",
416 "sdcard_d2",
417 "sdcard_d3",
418 "sdcard_cmd",
419 "sdcard_clk";
420 function = "sdcard";
421 };
422 };
423
424 sdio_pins: sdio {
425 mux {
426 groups = "sdio_d0",
427 "sdio_d1",
428 "sdio_d2",
429 "sdio_d3",
430 "sdio_cmd",
431 "sdio_clk";
432 function = "sdio";
433 };
434 };
435
436 sdio_irq_pins: sdio_irq {
437 mux {
438 groups = "sdio_irq";
439 function = "sdio";
440 };
441 };
442
443 uart_a_pins: uart_a {
444 mux {
445 groups = "uart_tx_a",
446 "uart_rx_a";
447 function = "uart_a";
448 };
449 };
450
451 uart_a_cts_rts_pins: uart_a_cts_rts {
452 mux {
453 groups = "uart_cts_a",
454 "uart_rts_a";
455 function = "uart_a";
456 };
457 };
458
459 uart_b_pins: uart_b {
460 mux {
461 groups = "uart_tx_b",
462 "uart_rx_b";
463 function = "uart_b";
464 };
465 };
466
467 uart_b_cts_rts_pins: uart_b_cts_rts {
468 mux {
469 groups = "uart_cts_b",
470 "uart_rts_b";
471 function = "uart_b";
472 };
473 };
474
475 uart_c_pins: uart_c {
476 mux {
477 groups = "uart_tx_c",
478 "uart_rx_c";
479 function = "uart_c";
480 };
481 };
482
483 uart_c_cts_rts_pins: uart_c_cts_rts {
484 mux {
485 groups = "uart_cts_c",
486 "uart_rts_c";
487 function = "uart_c";
488 };
489 };
490
491 i2c_a_pins: i2c_a {
492 mux {
493 groups = "i2c_sck_a",
494 "i2c_sda_a";
495 function = "i2c_a";
496 };
497 };
498
499 i2c_b_pins: i2c_b {
500 mux {
501 groups = "i2c_sck_b",
502 "i2c_sda_b";
503 function = "i2c_b";
504 };
505 };
506
507 i2c_c_pins: i2c_c {
508 mux {
509 groups = "i2c_sck_c",
510 "i2c_sda_c";
511 function = "i2c_c";
512 };
513 };
514
515 eth_rgmii_pins: eth-rgmii {
516 mux {
517 groups = "eth_mdio",
518 "eth_mdc",
519 "eth_clk_rx_clk",
520 "eth_rx_dv",
521 "eth_rxd0",
522 "eth_rxd1",
523 "eth_rxd2",
524 "eth_rxd3",
525 "eth_rgmii_tx_clk",
526 "eth_tx_en",
527 "eth_txd0",
528 "eth_txd1",
529 "eth_txd2",
530 "eth_txd3";
531 function = "eth";
532 };
533 };
534
535 eth_rmii_pins: eth-rmii {
536 mux {
537 groups = "eth_mdio",
538 "eth_mdc",
539 "eth_clk_rx_clk",
540 "eth_rx_dv",
541 "eth_rxd0",
542 "eth_rxd1",
543 "eth_tx_en",
544 "eth_txd0",
545 "eth_txd1";
546 function = "eth";
547 };
548 };
549
550 pwm_a_x_pins: pwm_a_x {
551 mux {
552 groups = "pwm_a_x";
553 function = "pwm_a_x";
554 };
555 };
556
557 pwm_a_y_pins: pwm_a_y {
558 mux {
559 groups = "pwm_a_y";
560 function = "pwm_a_y";
561 };
562 };
563
564 pwm_b_pins: pwm_b {
565 mux {
566 groups = "pwm_b";
567 function = "pwm_b";
568 };
569 };
570
571 pwm_d_pins: pwm_d {
572 mux {
573 groups = "pwm_d";
574 function = "pwm_d";
575 };
576 };
577
578 pwm_e_pins: pwm_e {
579 mux {
580 groups = "pwm_e";
581 function = "pwm_e";
582 };
583 };
584
585 pwm_f_x_pins: pwm_f_x {
586 mux {
587 groups = "pwm_f_x";
588 function = "pwm_f_x";
589 };
590 };
591
592 pwm_f_y_pins: pwm_f_y {
593 mux {
594 groups = "pwm_f_y";
595 function = "pwm_f_y";
596 };
597 };
598
599 hdmi_hpd_pins: hdmi_hpd {
600 mux {
601 groups = "hdmi_hpd";
602 function = "hdmi_hpd";
603 };
604 };
605
606 hdmi_i2c_pins: hdmi_i2c {
607 mux {
608 groups = "hdmi_sda", "hdmi_scl";
609 function = "hdmi_i2c";
610 };
611 };
Beniamino Galvani4a63a752017-07-10 00:30:03 +0200612
613 i2sout_ch23_y_pins: i2sout_ch23_y {
614 mux {
615 groups = "i2sout_ch23_y";
616 function = "i2s_out";
617 };
618 };
619
620 i2sout_ch45_y_pins: i2sout_ch45_y {
621 mux {
622 groups = "i2sout_ch45_y";
623 function = "i2s_out";
624 };
625 };
626
627 i2sout_ch67_y_pins: i2sout_ch67_y {
628 mux {
629 groups = "i2sout_ch67_y";
630 function = "i2s_out";
631 };
632 };
633
634 spdif_out_y_pins: spdif_out_y {
635 mux {
636 groups = "spdif_out_y";
637 function = "spdif_out";
638 };
639 };
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200640 };
641};
642
Beniamino Galvani4a63a752017-07-10 00:30:03 +0200643&saradc {
644 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
645 clocks = <&xtal>,
646 <&clkc CLKID_SAR_ADC>,
647 <&clkc CLKID_SANA>,
648 <&clkc CLKID_SAR_ADC_CLK>,
649 <&clkc CLKID_SAR_ADC_SEL>;
650 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
651};
652
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200653&sd_emmc_a {
654 clocks = <&clkc CLKID_SD_EMMC_A>,
655 <&xtal>,
656 <&clkc CLKID_FCLK_DIV2>;
657 clock-names = "core", "clkin0", "clkin1";
658};
659
660&sd_emmc_b {
661 clocks = <&clkc CLKID_SD_EMMC_B>,
662 <&xtal>,
663 <&clkc CLKID_FCLK_DIV2>;
664 clock-names = "core", "clkin0", "clkin1";
665};
666
667&sd_emmc_c {
668 clocks = <&clkc CLKID_SD_EMMC_C>,
669 <&xtal>,
670 <&clkc CLKID_FCLK_DIV2>;
671 clock-names = "core", "clkin0", "clkin1";
672};
673
Neil Armstrong48622152017-10-12 15:50:30 +0200674&spicc {
675 clocks = <&clkc CLKID_SPICC>;
676 clock-names = "core";
677 resets = <&reset RESET_PERIPHS_SPICC>;
678 num-cs = <1>;
679};
680
Beniamino Galvani4a63a752017-07-10 00:30:03 +0200681&spifc {
682 clocks = <&clkc CLKID_SPI>;
683};
684
Heiner Kallweita3b02a12017-04-12 20:28:36 +0200685&vpu {
686 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
Beniamino Galvanibfcef282016-05-08 08:30:16 +0200687};