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wdenkf7d15722004-12-18 22:35:43 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkf7d15722004-12-18 22:35:43 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf7d15722004-12-18 22:35:43 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC860 1
21#define CONFIG_MPC860T 1
22#define CONFIG_MPC862 1 /* enable 862 since the */
23#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */
24
25#define CONFIG_UC100 1 /* ...on a UC100 module */
26
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#define CONFIG_SYS_TEXT_BASE 0x40700000
28
wdenkf7d15722004-12-18 22:35:43 +000029#define MPC8XX_FACT 4 /* Multiply by 4 */
30#define MPC8XX_XIN 25000000 /* 25.0 MHz in */
31#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
32 /* define if cant' use get_gclk_freq */
33
34#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
35#undef CONFIG_8xx_CONS_SMC2
36#undef CONFIG_8xx_CONS_NONE
37
38#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
39
40#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
41
42#define CONFIG_BOOTCOUNT_LIMIT
43
44#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
45
46#define CONFIG_BOARD_TYPES 1 /* support board types */
47
48#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010049 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf7d15722004-12-18 22:35:43 +000050 "echo"
51
52#undef CONFIG_BOOTARGS
53
54#define CONFIG_EXTRA_ENV_SETTINGS \
55 "netdev=eth0\0" \
56 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010057 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf7d15722004-12-18 22:35:43 +000058 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010059 "addip=setenv bootargs ${bootargs} " \
60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
61 ":${hostname}:${netdev}:off panic=1\0" \
62 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
wdenkf7d15722004-12-18 22:35:43 +000063 "flash_nfs=run nfsargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010064 "bootm ${kernel_addr}\0" \
wdenkf7d15722004-12-18 22:35:43 +000065 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
67 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Wolfgang Denk93e14592013-10-04 17:43:24 +020068 "bootm\0" \
wdenkf7d15722004-12-18 22:35:43 +000069 "rootpath=/opt/eldk/ppc_8xx\0" \
70 "bootfile=/tftpboot/uc100/uImage\0" \
71 "kernel_addr=40000000\0" \
72 "ramdisk_addr=40100000\0" \
73 "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \
74 "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010075 "cp.b 100000 40700000 ${filesize};" \
wdenkf7d15722004-12-18 22:35:43 +000076 "setenv filesize;saveenv\0" \
77 ""
78#define CONFIG_BOOTCOMMAND "run flash_self"
79
80#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf7d15722004-12-18 22:35:43 +000082
83#undef CONFIG_WATCHDOG /* watchdog disabled */
84
85#undef CONFIG_STATUS_LED /* no status-led */
86
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050087/*
88 * BOOTP options
89 */
90#define CONFIG_BOOTP_SUBNETMASK
91#define CONFIG_BOOTP_GATEWAY
92#define CONFIG_BOOTP_HOSTNAME
93#define CONFIG_BOOTP_BOOTPATH
94#define CONFIG_BOOTP_BOOTFILESIZE
95
wdenkf7d15722004-12-18 22:35:43 +000096
97#define CONFIG_MAC_PARTITION
98#define CONFIG_DOS_PARTITION
99
100#undef CONFIG_RTC_MPC8xx
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
wdenkf7d15722004-12-18 22:35:43 +0000102#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
103
104/*
105 * Power On Self Test support
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \
108 CONFIG_SYS_POST_MEMORY | \
109 CONFIG_SYS_POST_CPU | \
110 CONFIG_SYS_POST_UART | \
111 CONFIG_SYS_POST_SPR )
wdenkf7d15722004-12-18 22:35:43 +0000112#undef CONFIG_POST
113
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500114
115/*
116 * Command line configuration.
117 */
118#include <config_cmd_default.h>
119
120#define CONFIG_CMD_ASKENV
121#define CONFIG_CMD_DATE
122#define CONFIG_CMD_DHCP
123#define CONFIG_CMD_EEPROM
124#define CONFIG_CMD_ELF
125#define CONFIG_CMD_FAT
126#define CONFIG_CMD_I2C
127#define CONFIG_CMD_IDE
128#define CONFIG_CMD_MII
129#define CONFIG_CMD_NFS
130#define CONFIG_CMD_PING
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500131#define CONFIG_CMD_SNTP
132
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500133#ifdef CONFIG_POST
134#define CONFIG_CMD_DIAG
135#endif
136
wdenkf7d15722004-12-18 22:35:43 +0000137
138#define CONFIG_NETCONSOLE
139
wdenkf7d15722004-12-18 22:35:43 +0000140/*
141 * Miscellaneous configurable options
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkf7d15722004-12-18 22:35:43 +0000144
145#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
wdenkf7d15722004-12-18 22:35:43 +0000147#endif
wdenkf7d15722004-12-18 22:35:43 +0000148
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500149#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf7d15722004-12-18 22:35:43 +0000151#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf7d15722004-12-18 22:35:43 +0000153#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
155#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
156#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf7d15722004-12-18 22:35:43 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
159#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf7d15722004-12-18 22:35:43 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf7d15722004-12-18 22:35:43 +0000162
wdenkf7d15722004-12-18 22:35:43 +0000163#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
164
165/*
166 * Low Level Configuration Settings
167 * (address mappings, register initial values, etc.)
168 * You should know what you are doing if you make changes here.
169 */
170/*-----------------------------------------------------------------------
171 * Internal Memory Mapped Register
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_IMMR 0xF0000000
wdenkf7d15722004-12-18 22:35:43 +0000174
175/*-----------------------------------------------------------------------
176 * Definitions for initial stack pointer and data area (in DPRAM)
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200179#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200180#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf7d15722004-12-18 22:35:43 +0000182
183/*-----------------------------------------------------------------------
184 * Start addresses for the final memory configuration
185 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf7d15722004-12-18 22:35:43 +0000187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_SDRAM_BASE 0x00000000
189#define CONFIG_SYS_FLASH_BASE 0x40000000
190#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
191#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/
192#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf7d15722004-12-18 22:35:43 +0000193
194/*-----------------------------------------------------------------------
195 * Address accessed to reset the board - must not be mapped/assigned
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_RESET_ADDRESS 0x90000000
wdenkf7d15722004-12-18 22:35:43 +0000198
199/*
200 * For booting Linux, the board info and command line data
201 * have to be in the first 8 MB of memory, since this is
202 * the maximum mapped by the Linux kernel during initialization.
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf7d15722004-12-18 22:35:43 +0000205
206/*-----------------------------------------------------------------------
207 * FLASH organization
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200210#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
wdenkf7d15722004-12-18 22:35:43 +0000212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
214#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf7d15722004-12-18 22:35:43 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
217#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkf7d15722004-12-18 22:35:43 +0000218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkf7d15722004-12-18 22:35:43 +0000220
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200221#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200223#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
224#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf7d15722004-12-18 22:35:43 +0000225
226/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200227#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
228#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf7d15722004-12-18 22:35:43 +0000229
230/*-----------------------------------------------------------------------
231 * Cache Configuration
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger6c18eb92007-07-04 22:33:38 -0500234#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf7d15722004-12-18 22:35:43 +0000236#endif
237
238/*-----------------------------------------------------------------------
239 * SYPCR - System Protection Control 11-9
240 * SYPCR can only be written once after reset!
241 *-----------------------------------------------------------------------
242 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
243 */
244#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf7d15722004-12-18 22:35:43 +0000246 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
247#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf7d15722004-12-18 22:35:43 +0000249#endif
250
251/*-----------------------------------------------------------------------
252 * SIUMCR - SIU Module Configuration 11-6
253 *-----------------------------------------------------------------------
254 * PCMCIA config., multi-function pin tri-state
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf7d15722004-12-18 22:35:43 +0000257
258/*-----------------------------------------------------------------------
259 * TBSCR - Time Base Status and Control 11-26
260 *-----------------------------------------------------------------------
261 * Clear Reference Interrupt Status, Timebase freezing enabled
262 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf7d15722004-12-18 22:35:43 +0000264
265/*-----------------------------------------------------------------------
266 * RTCSC - Real-Time Clock Status and Control Register 11-27
267 *-----------------------------------------------------------------------
268 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf7d15722004-12-18 22:35:43 +0000270
271/*-----------------------------------------------------------------------
272 * PISCR - Periodic Interrupt Status and Control 11-31
273 *-----------------------------------------------------------------------
274 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf7d15722004-12-18 22:35:43 +0000277
278/*-----------------------------------------------------------------------
279 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
280 *-----------------------------------------------------------------------
281 * Reset PLL lock status sticky bit, timer expired status bit and timer
282 * interrupt status bit
283 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
wdenkf7d15722004-12-18 22:35:43 +0000285 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
286
287/*-----------------------------------------------------------------------
288 * SCCR - System Clock and reset Control Register 15-27
289 *-----------------------------------------------------------------------
290 * Set clock output, timebase and RTC source and divider,
291 * power management and some other internal clocks
292 */
293#define SCCR_MASK 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_SCCR (SCCR_EBDF11)
wdenkf7d15722004-12-18 22:35:43 +0000295
296/*-----------------------------------------------------------------------
297 * PCMCIA stuff
298 *-----------------------------------------------------------------------
299 *
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
302#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
303#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
304#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
305#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
306#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
307#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
308#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf7d15722004-12-18 22:35:43 +0000309
310/*-----------------------------------------------------------------------
311 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
312 *-----------------------------------------------------------------------
313 */
314
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000315#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf7d15722004-12-18 22:35:43 +0000316#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
317
318#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
319#undef CONFIG_IDE_LED /* LED for ide not supported */
320#undef CONFIG_IDE_RESET /* reset for ide not supported */
321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
323#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf7d15722004-12-18 22:35:43 +0000324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf7d15722004-12-18 22:35:43 +0000326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf7d15722004-12-18 22:35:43 +0000328
329/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf7d15722004-12-18 22:35:43 +0000331
332/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf7d15722004-12-18 22:35:43 +0000334
335/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf7d15722004-12-18 22:35:43 +0000337
338/*-----------------------------------------------------------------------
339 *
340 *-----------------------------------------------------------------------
341 *
342 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_DER 0
wdenkf7d15722004-12-18 22:35:43 +0000344
345/*
346 * Init Memory Controller:
347 *
348 * BR0/1 and OR0/1 (FLASH)
349 */
350
351#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
352#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
353
354/* used to re-map FLASH both when starting from SRAM or FLASH:
355 * restrict access enough to keep SRAM working (if any)
356 * but not too much to meddle with FLASH accesses
357 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
359#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
wdenkf7d15722004-12-18 22:35:43 +0000360
361/*
362 * FLASH timing:
363 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_OR_TIMING_FLASH (0x00000d24)
wdenkf7d15722004-12-18 22:35:43 +0000365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
367#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
368#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf7d15722004-12-18 22:35:43 +0000369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
371#define CONFIG_SYS_OR1_PRELIM 0xfc000a00
372#define CONFIG_SYS_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
373#define CONFIG_SYS_OR2_PRELIM 0xfff00d24
374#define CONFIG_SYS_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
375#define CONFIG_SYS_OR3_PRELIM 0xffff8f44
376#define CONFIG_SYS_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
377#define CONFIG_SYS_OR4_PRELIM 0xffff0300
378#define CONFIG_SYS_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
379#define CONFIG_SYS_OR5_PRELIM 0xffff8db0
wdenkf7d15722004-12-18 22:35:43 +0000380
381/*
382 * Memory Periodic Timer Prescaler
383 *
384 * The Divider for PTA (refresh timer) configuration is based on an
385 * example SDRAM configuration (64 MBit, one bank). The adjustment to
386 * the number of chip selects (NCS) and the actually needed refresh
387 * rate is done by setting MPTPR.
388 *
389 * PTA is calculated from
390 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
391 *
392 * gclk CPU clock (not bus clock!)
393 * Trefresh Refresh cycle * 4 (four word bursts used)
394 *
395 * 4096 Rows from SDRAM example configuration
396 * 1000 factor s -> ms
397 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
398 * 4 Number of refresh cycles per period
399 * 64 Refresh cycle in ms per number of rows
400 * --------------------------------------------
401 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
402 *
403 * 50 MHz => 50.000.000 / Divider = 98
404 * 66 Mhz => 66.000.000 / Divider = 129
405 * 80 Mhz => 80.000.000 / Divider = 156
406 * 100 Mhz => 100.000.000 / Divider = 195
407 */
408
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
410#define CONFIG_SYS_MAMR_PTA 98
wdenkf7d15722004-12-18 22:35:43 +0000411
412/*
413 * For 16 MBit, refresh rates could be 31.3 us
414 * (= 64 ms / 2K = 125 / quad bursts).
415 * For a simpler initialization, 15.6 us is used instead.
416 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
418 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf7d15722004-12-18 22:35:43 +0000419 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
421#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf7d15722004-12-18 22:35:43 +0000422
423/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
425#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf7d15722004-12-18 22:35:43 +0000426
427/*
428 * MAMR settings for SDRAM
429 */
430
431/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf7d15722004-12-18 22:35:43 +0000433 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
434 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
435/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf7d15722004-12-18 22:35:43 +0000437 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
438 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
439
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_MAMR_VAL 0x30904114 /* for SDRAM */
441#define CONFIG_SYS_MBMR_VAL 0xff001111 /* for Interbus-MPM */
wdenkf7d15722004-12-18 22:35:43 +0000442
443/*-----------------------------------------------------------------------
444 * I2C stuff
445 */
446
447/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +0100448#define CONFIG_SYS_I2C
449#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
450#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
451#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenkf7d15722004-12-18 22:35:43 +0000452/*
453 * Software (bit-bang) I2C driver configuration
454 */
455#define PB_SCL 0x00000020 /* PB 26 */
456#define PB_SDA 0x00000010 /* PB 27 */
457
458#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
459#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
460#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
461#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
462#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
463 else immr->im_cpm.cp_pbdat &= ~PB_SDA
464#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
465 else immr->im_cpm.cp_pbdat &= ~PB_SCL
466#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
wdenkf7d15722004-12-18 22:35:43 +0000467
468/*-----------------------------------------------------------------------
469 * I2C EEPROM (24C164)
470 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
472#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
473#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
474#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
wdenkf7d15722004-12-18 22:35:43 +0000475
wdenkf7d15722004-12-18 22:35:43 +0000476#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
477#define FEC_ENET
478#define CONFIG_MII
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500479#define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_DISCOVER_PHY 1
wdenkf7d15722004-12-18 22:35:43 +0000481
482#endif /* __CONFIG_H */