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Lokesh Vutla853f7f52018-08-27 15:59:09 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
Andreas Dannenberg7202af92019-04-29 12:56:44 -05006#include <dt-bindings/pinctrl/k3.h>
Grygorii Strashko6f2929d2019-07-09 10:30:36 +05307#include <dt-bindings/net/ti-dp83867.h>
Lokesh Vutla853f7f52018-08-27 15:59:09 +05308
9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
12 };
13
14 aliases {
15 serial2 = &main_uart0;
Grygorii Strashko5195c102019-07-09 10:30:35 +053016 ethernet0 = &cpsw_port1;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053017 };
18};
19
20&cbass_main{
21 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053022
Lokesh Vutla853f7f52018-08-27 15:59:09 +053023 sdhci1: sdhci@04FA0000 {
Faiz Abbas3a1a0df2019-06-11 00:43:31 +053024 compatible = "ti,am654-sdhci-5.1";
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053025 reg = <0x0 0x4FA0000 0x0 0x1000>,
26 <0x0 0x4FB0000 0x0 0x400>;
Faiz Abbasfe0e30c2020-01-16 19:42:18 +053027 clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
28 clock-names = "clk_ahb", "clk_xin";
Lokesh Vutla355be912019-06-07 19:24:47 +053029 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053030 max-frequency = <25000000>;
Faiz Abbasc7d106b2020-02-26 13:44:33 +053031 ti,otap-del-sel-legacy = <0x0>;
32 ti,otap-del-sel-mmc-hs = <0x0>;
33 ti,otap-del-sel-sd-hs = <0x0>;
34 ti,otap-del-sel-sdr12 = <0x0>;
35 ti,otap-del-sel-sdr25 = <0x0>;
36 ti,otap-del-sel-sdr50 = <0x8>;
37 ti,otap-del-sel-sdr104 = <0x7>;
38 ti,otap-del-sel-ddr50 = <0x4>;
39 ti,otap-del-sel-ddr52 = <0x4>;
40 ti,otap-del-sel-hs200 = <0x7>;
Faiz Abbasbbcfaad2019-06-11 00:43:36 +053041 ti,trm-icp = <0x8>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053042 };
43
44};
45
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053046&cbass_mcu {
47 u-boot,dm-spl;
Grygorii Strashko736b6c32019-02-05 17:31:26 +053048
Vignesh Raghavendra99faf0d2020-07-07 13:43:35 +053049 mcu_navss {
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +053050 u-boot,dm-spl;
Grygorii Strashko736b6c32019-02-05 17:31:26 +053051
Vignesh Raghavendra99faf0d2020-07-07 13:43:35 +053052 ringacc@2b800000 {
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +053053 u-boot,dm-spl;
Grygorii Strashko736b6c32019-02-05 17:31:26 +053054 };
55
Vignesh Raghavendra99faf0d2020-07-07 13:43:35 +053056 dma-controller@285c0000 {
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +053057 u-boot,dm-spl;
Grygorii Strashko736b6c32019-02-05 17:31:26 +053058 };
59 };
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053060};
61
62&cbass_wakeup {
63 u-boot,dm-spl;
64};
65
66&secure_proxy_main {
Lokesh Vutla853f7f52018-08-27 15:59:09 +053067 u-boot,dm-spl;
68};
69
70&dmsc {
71 u-boot,dm-spl;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053072 k3_sysreset: sysreset-controller {
73 compatible = "ti,sci-sysreset";
74 u-boot,dm-spl;
75 };
Lokesh Vutla853f7f52018-08-27 15:59:09 +053076};
77
78&k3_pds {
79 u-boot,dm-spl;
80};
81
82&k3_clks {
83 u-boot,dm-spl;
84};
85
86&k3_reset {
87 u-boot,dm-spl;
88};
89
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -050090&wkup_pmx0 {
91 u-boot,dm-spl;
92
93 wkup_i2c0_pins_default {
94 u-boot,dm-spl;
95 };
96};
97
Lokesh Vutla853f7f52018-08-27 15:59:09 +053098&main_pmx0 {
99 u-boot,dm-spl;
100 main_uart0_pins_default: main_uart0_pins_default {
101 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500102 AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
103 AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
104 AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
105 AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530106 >;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530107 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530108 };
109
110 main_mmc0_pins_default: main_mmc0_pins_default {
111 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500112 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
113 AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
114 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
115 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
116 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
117 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
118 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
119 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
120 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
121 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530122 AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
123 AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530124 >;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530125 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530126 };
127
128 main_mmc1_pins_default: main_mmc1_pins_default {
129 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500130 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
131 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
132 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
133 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
134 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
135 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
136 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
137 AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530138 >;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530139 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530140 };
141
142};
143
144&main_pmx1 {
145 u-boot,dm-spl;
146};
147
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530148&wkup_pmx0 {
149 mcu_cpsw_pins_default: mcu_cpsw_pins_default {
150 pinctrl-single,pins = <
151 AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
152 AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
153 AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
154 AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
155 AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
156 AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
157 AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
158 AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
159 AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
160 AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
161 AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
162 AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
163 >;
164 };
165
166 mcu_mdio_pins_default: mcu_mdio1_pins_default {
167 pinctrl-single,pins = <
168 AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
169 AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
170 >;
171 };
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +0530172
173 mcu-fss0-ospi0-pins-default {
174 u-boot,dm-spl;
175 };
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530176};
177
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530178&main_uart0 {
179 u-boot,dm-spl;
180 pinctrl-names = "default";
181 pinctrl-0 = <&main_uart0_pins_default>;
182 status = "okay";
183};
184
185&sdhci0 {
186 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530187};
188
189&sdhci1 {
190 u-boot,dm-spl;
191 status = "okay";
192 pinctrl-names = "default";
193 pinctrl-0 = <&main_mmc1_pins_default>;
194 sdhci-caps-mask = <0x7 0x0>;
Faiz Abbasbbcfaad2019-06-11 00:43:36 +0530195 ti,driver-strength-ohm = <50>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530196};
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530197
198&mcu_cpsw {
199 pinctrl-names = "default";
200 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
201};
202
203&davinci_mdio {
204 phy0: ethernet-phy@0 {
205 reg = <0>;
206 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
207 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530208 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
209 };
210};
211
212&cpsw_port1 {
Grygorii Strashko5efb6922019-11-18 23:04:47 +0200213 phy-mode = "rgmii-rxid";
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530214 phy-handle = <&phy0>;
215};
216
217&mcu_cpsw {
218 reg = <0x0 0x46000000 0x0 0x200000>,
219 <0x0 0x40f00200 0x0 0x2>;
220 reg-names = "cpsw_nuss", "mac_efuse";
Vignesh Raghavendra3f09ebf2020-07-06 13:36:56 +0530221 /delete-property/ ranges;
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530222
223 cpsw-phy-sel@40f04040 {
224 compatible = "ti,am654-cpsw-phy-sel";
225 reg= <0x0 0x40f04040 0x0 0x4>;
226 reg-names = "gmii-sel";
227 };
228};
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500229
230&wkup_i2c0 {
231 u-boot,dm-spl;
232};
Vignesh Raghavendra60120072019-12-09 10:37:33 +0530233
234&usb1 {
235 dr_mode = "peripheral";
236};
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +0530237
238&fss {
239 u-boot,dm-spl;
240};
241
242&ospi0 {
243 u-boot,dm-spl;
244
245 flash@0{
246 u-boot,dm-spl;
247 };
248};