blob: 0133eaa2ca9fc9ce2bb33db1d1e8c017e04c6517 [file] [log] [blame]
Heiko Schocher6341d9d2008-01-11 15:15:14 +01001/*
2 * (C) Copyright 2004
3 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher6341d9d2008-01-11 15:15:14 +01006 */
7
8#define SDRAM_DDR 0 /* is SDR */
9
Heiko Schocher6341d9d2008-01-11 15:15:14 +010010/* Settings for XLB = 132 MHz */
11#define SDRAM_MODE 0x00CD0000
12#define SDRAM_CONTROL 0x504F0000
13#define SDRAM_CONFIG1 0xD2322800
14#define SDRAM_CONFIG2 0x8AD70000