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Prafulla Wadaskar91315892009-06-14 22:33:46 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * based on - Driver for MV64360X ethernet ports
7 * Copyright (C) 2002 rabeeh@galileo.co.il
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar91315892009-06-14 22:33:46 +053010 */
11
Albert Aribaudd44265a2010-07-12 22:24:28 +020012#ifndef __MVGBE_H__
13#define __MVGBE_H__
Prafulla Wadaskar91315892009-06-14 22:33:46 +053014
Prafulla Wadaskar91315892009-06-14 22:33:46 +053015/* PHY_BASE_ADR is board specific and can be configured */
16#if defined (CONFIG_PHY_BASE_ADR)
17#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
18#else
19#define PHY_BASE_ADR 0x08 /* default phy base addr */
20#endif
21
22/* Constants */
23#define INT_CAUSE_UNMASK_ALL 0x0007ffff
24#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
25#define MRU_MASK 0xfff1ffff
26#define PHYADR_MASK 0x0000001f
27#define PHYREG_MASK 0x0000001f
28#define QTKNBKT_DEF_VAL 0x3fffffff
29#define QMTBS_DEF_VAL 0x000003ff
30#define QTKNRT_DEF_VAL 0x0000fcff
31#define RXUQ 0 /* Used Rx queue */
32#define TXUQ 0 /* Used Rx queue */
33
Albert Aribaudd44265a2010-07-12 22:24:28 +020034#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
35#define MVGBE_REG_WR(adr, val) writel(val, &adr)
36#define MVGBE_REG_RD(adr) readl(&adr)
37#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
38#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053039
40/* Default port configuration value */
41#define PRT_CFG_VAL ( \
Albert Aribaudd44265a2010-07-12 22:24:28 +020042 MVGBE_UCAST_MOD_NRML | \
43 MVGBE_DFLT_RXQ(RXUQ) | \
44 MVGBE_DFLT_RX_ARPQ(RXUQ) | \
45 MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \
46 MVGBE_RX_BC_IF_IP | \
47 MVGBE_RX_BC_IF_ARP | \
48 MVGBE_CPTR_TCP_FRMS_DIS | \
49 MVGBE_CPTR_UDP_FRMS_DIS | \
50 MVGBE_DFLT_RX_TCPQ(RXUQ) | \
51 MVGBE_DFLT_RX_UDPQ(RXUQ) | \
52 MVGBE_DFLT_RX_BPDUQ(RXUQ))
Prafulla Wadaskar91315892009-06-14 22:33:46 +053053
54/* Default port extend configuration value */
55#define PORT_CFG_EXTEND_VALUE \
Albert Aribaudd44265a2010-07-12 22:24:28 +020056 MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
57 MVGBE_PARTITION_DIS | \
58 MVGBE_TX_CRC_GENERATION_EN
Prafulla Wadaskar91315892009-06-14 22:33:46 +053059
Albert Aribaudd44265a2010-07-12 22:24:28 +020060#define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053061
62/* Default sdma control value */
63#define PORT_SDMA_CFG_VALUE ( \
Albert Aribaudd44265a2010-07-12 22:24:28 +020064 MVGBE_RX_BURST_SIZE_16_64BIT | \
65 MVGBE_BLM_RX_NO_SWAP | \
66 MVGBE_BLM_TX_NO_SWAP | \
67 GT_MVGBE_IPG_INT_RX(RXUQ) | \
68 MVGBE_TX_BURST_SIZE_16_64BIT)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053069
70/* Default port serial control value */
Valentin Longchampd3920142011-05-31 02:12:51 +000071#ifndef PORT_SERIAL_CONTROL_VALUE
Prafulla Wadaskar91315892009-06-14 22:33:46 +053072#define PORT_SERIAL_CONTROL_VALUE ( \
Albert Aribaudd44265a2010-07-12 22:24:28 +020073 MVGBE_FORCE_LINK_PASS | \
74 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
75 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
76 MVGBE_ADV_NO_FLOW_CTRL | \
77 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
78 MVGBE_FORCE_BP_MODE_NO_JAM | \
Prafulla Wadaskar91315892009-06-14 22:33:46 +053079 (1 << 9) /* Reserved bit has to be 1 */ | \
Albert Aribaudd44265a2010-07-12 22:24:28 +020080 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
81 MVGBE_EN_AUTO_NEG_SPEED_GMII | \
82 MVGBE_DTE_ADV_0 | \
83 MVGBE_MIIPHY_MAC_MODE | \
84 MVGBE_AUTO_NEG_NO_CHANGE | \
85 MVGBE_MAX_RX_PACKET_1552BYTE | \
86 MVGBE_CLR_EXT_LOOPBACK | \
87 MVGBE_SET_FULL_DUPLEX_MODE | \
88 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
Valentin Longchampd3920142011-05-31 02:12:51 +000089#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +053090
91/* Tx WRR confoguration macros */
92#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
93#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
94#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
95/* MAC accepet/reject macros */
96#define ACCEPT_MAC_ADDR 0
97#define REJECT_MAC_ADDR 1
98/* Size of a Tx/Rx descriptor used in chain list data structure */
Albert Aribaudd44265a2010-07-12 22:24:28 +020099#define MV_RXQ_DESC_ALIGNED_SIZE \
100 (((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530101/* Buffer offset from buffer pointer */
102#define RX_BUF_OFFSET 0x2
103
104/* Port serial status reg (PSR) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200105#define MVGBE_INTERFACE_GMII_MII 0
106#define MVGBE_INTERFACE_PCM 1
107#define MVGBE_LINK_IS_DOWN 0
108#define MVGBE_LINK_IS_UP (1 << 1)
109#define MVGBE_PORT_AT_HALF_DUPLEX 0
110#define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2)
111#define MVGBE_RX_FLOW_CTRL_DISD 0
112#define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
113#define MVGBE_GMII_SPEED_100_10 0
114#define MVGBE_GMII_SPEED_1000 (1 << 4)
115#define MVGBE_MII_SPEED_10 0
116#define MVGBE_MII_SPEED_100 (1 << 5)
117#define MVGBE_NO_TX 0
118#define MVGBE_TX_IN_PROGRESS (1 << 7)
119#define MVGBE_BYPASS_NO_ACTIVE 0
120#define MVGBE_BYPASS_ACTIVE (1 << 8)
121#define MVGBE_PORT_NOT_AT_PARTN_STT 0
122#define MVGBE_PORT_AT_PARTN_STT (1 << 9)
123#define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0
124#define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530125
126/* These macros describes the Port configuration reg (Px_cR) bits */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200127#define MVGBE_UCAST_MOD_NRML 0
128#define MVGBE_UNICAST_PROMISCUOUS_MODE 1
129#define MVGBE_DFLT_RXQ(_x) (_x << 1)
130#define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4)
131#define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0
132#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
133#define MVGBE_RX_BC_IF_IP 0
134#define MVGBE_REJECT_BC_IF_IP (1 << 8)
135#define MVGBE_RX_BC_IF_ARP 0
136#define MVGBE_REJECT_BC_IF_ARP (1 << 9)
137#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
138#define MVGBE_CPTR_TCP_FRMS_DIS 0
139#define MVGBE_CPTR_TCP_FRMS_EN (1 << 14)
140#define MVGBE_CPTR_UDP_FRMS_DIS 0
141#define MVGBE_CPTR_UDP_FRMS_EN (1 << 15)
142#define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16)
143#define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19)
144#define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
145#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530146
147/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
Albert Aribaudd44265a2010-07-12 22:24:28 +0200148#define MVGBE_CLASSIFY_EN 1
149#define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
150#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
151#define MVGBE_PARTITION_DIS 0
152#define MVGBE_PARTITION_EN (1 << 2)
153#define MVGBE_TX_CRC_GENERATION_EN 0
154#define MVGBE_TX_CRC_GENERATION_DIS (1 << 3)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530155
156/* These macros describes the Port Sdma configuration reg (SDCR) bits */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200157#define MVGBE_RIFB 1
158#define MVGBE_RX_BURST_SIZE_1_64BIT 0
159#define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
160#define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
161#define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
162#define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
163#define MVGBE_BLM_RX_NO_SWAP (1 << 4)
164#define MVGBE_BLM_RX_BYTE_SWAP 0
165#define MVGBE_BLM_TX_NO_SWAP (1 << 5)
166#define MVGBE_BLM_TX_BYTE_SWAP 0
167#define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
168#define MVGBE_DESCRIPTORS_NO_SWAP 0
169#define MVGBE_TX_BURST_SIZE_1_64BIT 0
170#define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
171#define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
172#define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
173#define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530174
175/* These macros describes the Port serial control reg (PSCR) bits */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200176#define MVGBE_SERIAL_PORT_DIS 0
177#define MVGBE_SERIAL_PORT_EN 1
178#define MVGBE_FORCE_LINK_PASS (1 << 1)
179#define MVGBE_DO_NOT_FORCE_LINK_PASS 0
180#define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0
181#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
182#define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
183#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
184#define MVGBE_ADV_NO_FLOW_CTRL 0
185#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
186#define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
187#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
188#define MVGBE_FORCE_BP_MODE_NO_JAM 0
189#define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
190#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
191#define MVGBE_FORCE_LINK_FAIL 0
192#define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
193#define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
194#define MVGBE_EN_AUTO_NEG_SPEED_GMII 0
195#define MVGBE_DTE_ADV_0 0
196#define MVGBE_DTE_ADV_1 (1 << 14)
197#define MVGBE_MIIPHY_MAC_MODE 0
198#define MVGBE_MIIPHY_PHY_MODE (1 << 15)
199#define MVGBE_AUTO_NEG_NO_CHANGE 0
200#define MVGBE_RESTART_AUTO_NEG (1 << 16)
201#define MVGBE_MAX_RX_PACKET_1518BYTE 0
202#define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
203#define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
204#define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
205#define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
206#define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
207#define MVGBE_SET_EXT_LOOPBACK (1 << 20)
208#define MVGBE_CLR_EXT_LOOPBACK 0
209#define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21)
210#define MVGBE_SET_HALF_DUPLEX_MODE 0
211#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
212#define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
213#define MVGBE_SET_GMII_SPEED_TO_10_100 0
214#define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
215#define MVGBE_SET_MII_SPEED_TO_10 0
216#define MVGBE_SET_MII_SPEED_TO_100 (1 << 24)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530217
218/* SMI register fields */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200219#define MVGBE_PHY_SMI_TIMEOUT 10000
220#define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */
221#define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS)
222#define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
223#define MVGBE_PHY_SMI_DEV_ADDR_MASK \
224 (PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
225#define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
226#define MVGBE_SMI_REG_ADDR_MASK \
227 (PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
228#define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
229#define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS)
230#define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS)
231#define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS)
232#define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
233#define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530234
235/* SDMA command status fields macros */
236/* Tx & Rx descriptors status */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200237#define MVGBE_ERROR_SUMMARY 1
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530238/* Tx & Rx descriptors command */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200239#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530240/* Tx descriptors status */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200241#define MVGBE_LC_ERROR 0
242#define MVGBE_UR_ERROR (1 << 1)
243#define MVGBE_RL_ERROR (1 << 2)
244#define MVGBE_LLC_SNAP_FORMAT (1 << 9)
245#define MVGBE_TX_LAST_FRAME (1 << 20)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530246
247/* Rx descriptors status */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200248#define MVGBE_CRC_ERROR 0
249#define MVGBE_OVERRUN_ERROR (1 << 1)
250#define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
251#define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
252#define MVGBE_VLAN_TAGGED (1 << 19)
253#define MVGBE_BPDU_FRAME (1 << 20)
254#define MVGBE_TCP_FRAME_OVER_IP_V_4 0
255#define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
256#define MVGBE_OTHER_FRAME_TYPE (1 << 22)
257#define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23)
258#define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24)
259#define MVGBE_FRAME_HEADER_OK (1 << 25)
260#define MVGBE_RX_LAST_DESC (1 << 26)
261#define MVGBE_RX_FIRST_DESC (1 << 27)
262#define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
263#define MVGBE_RX_EN_INTERRUPT (1 << 29)
264#define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530265
266/* Rx descriptors byte count */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200267#define MVGBE_FRAME_FRAGMENTED (1 << 2)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530268
269/* Tx descriptors command */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200270#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
271#define MVGBE_FRAME_SET_TO_VLAN (1 << 15)
272#define MVGBE_TCP_FRAME 0
273#define MVGBE_UDP_FRAME (1 << 16)
274#define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
275#define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
276#define MVGBE_ZERO_PADDING (1 << 19)
277#define MVGBE_TX_LAST_DESC (1 << 20)
278#define MVGBE_TX_FIRST_DESC (1 << 21)
279#define MVGBE_GEN_CRC (1 << 22)
280#define MVGBE_TX_EN_INTERRUPT (1 << 23)
281#define MVGBE_AUTO_MODE (1 << 30)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530282
283/* Address decode parameters */
284/* Ethernet Base Address Register bits */
285#define EBAR_TARGET_DRAM 0x00000000
286#define EBAR_TARGET_DEVICE 0x00000001
287#define EBAR_TARGET_CBS 0x00000002
288#define EBAR_TARGET_PCI0 0x00000003
289#define EBAR_TARGET_PCI1 0x00000004
290#define EBAR_TARGET_CUNIT 0x00000005
291#define EBAR_TARGET_AUNIT 0x00000006
292#define EBAR_TARGET_GUNIT 0x00000007
293
294/* Window attrib */
Sebastian Hesselbarthfb4879b2012-12-04 09:32:01 +0100295#if defined(CONFIG_DOVE)
296#define EBAR_DRAM_CS0 0x00000000
297#define EBAR_DRAM_CS1 0x00000000
298#define EBAR_DRAM_CS2 0x00000000
299#define EBAR_DRAM_CS3 0x00000000
300#else
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530301#define EBAR_DRAM_CS0 0x00000E00
302#define EBAR_DRAM_CS1 0x00000D00
303#define EBAR_DRAM_CS2 0x00000B00
304#define EBAR_DRAM_CS3 0x00000700
Sebastian Hesselbarthfb4879b2012-12-04 09:32:01 +0100305#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530306
307/* DRAM Target interface */
308#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
309#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
310#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
311
312/* Device Bus Target interface */
313#define EBAR_DEVICE_DEVCS0 0x00001E00
314#define EBAR_DEVICE_DEVCS1 0x00001D00
315#define EBAR_DEVICE_DEVCS2 0x00001B00
316#define EBAR_DEVICE_DEVCS3 0x00001700
317#define EBAR_DEVICE_BOOTCS3 0x00000F00
318
319/* PCI Target interface */
320#define EBAR_PCI_BYTE_SWAP 0x00000000
321#define EBAR_PCI_NO_SWAP 0x00000100
322#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
323#define EBAR_PCI_WORD_SWAP 0x00000300
324#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
325#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
326#define EBAR_PCI_IO_SPACE 0x00000000
327#define EBAR_PCI_MEMORY_SPACE 0x00000800
328#define EBAR_PCI_REQ64_FORCE 0x00000000
329#define EBAR_PCI_REQ64_SIZE 0x00001000
330
331/* Window access control */
332#define EWIN_ACCESS_NOT_ALLOWED 0
333#define EWIN_ACCESS_READ_ONLY 1
334#define EWIN_ACCESS_FULL ((1 << 1) | 1)
335
336/* structures represents Controller registers */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200337struct mvgbe_barsz {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530338 u32 bar;
339 u32 size;
340};
341
Albert Aribaudd44265a2010-07-12 22:24:28 +0200342struct mvgbe_rxcdp {
343 struct mvgbe_rxdesc *rxcdp;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530344 u32 rxcdp_pad[3];
345};
346
Albert Aribaudd44265a2010-07-12 22:24:28 +0200347struct mvgbe_tqx {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530348 u32 qxttbc;
349 u32 tqxtbc;
350 u32 tqxac;
351 u32 tqxpad;
352};
353
Albert Aribaudd44265a2010-07-12 22:24:28 +0200354struct mvgbe_registers {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530355 u32 phyadr;
356 u32 smi;
357 u32 euda;
358 u32 eudid;
359 u8 pad1[0x080 - 0x00c - 4];
360 u32 euic;
361 u32 euim;
362 u8 pad2[0x094 - 0x084 - 4];
363 u32 euea;
364 u32 euiae;
365 u8 pad3[0x0b0 - 0x098 - 4];
366 u32 euc;
367 u8 pad3a[0x200 - 0x0b0 - 4];
Albert Aribaudd44265a2010-07-12 22:24:28 +0200368 struct mvgbe_barsz barsz[6];
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530369 u8 pad4[0x280 - 0x22c - 4];
370 u32 ha_remap[4];
371 u32 bare;
372 u32 epap;
373 u8 pad5[0x400 - 0x294 - 4];
374 u32 pxc;
375 u32 pxcx;
376 u32 mii_ser_params;
377 u8 pad6[0x410 - 0x408 - 4];
378 u32 evlane;
379 u32 macal;
380 u32 macah;
381 u32 sdc;
382 u32 dscp[7];
383 u32 psc0;
384 u32 vpt2p;
385 u32 ps0;
386 u32 tqc;
387 u32 psc1;
388 u32 ps1;
389 u32 mrvl_header;
390 u8 pad7[0x460 - 0x454 - 4];
391 u32 ic;
392 u32 ice;
393 u32 pim;
394 u32 peim;
395 u8 pad8[0x474 - 0x46c - 4];
396 u32 pxtfut;
397 u32 pad9;
398 u32 pxmfs;
399 u32 pad10;
400 u32 pxdfc;
401 u32 pxofc;
402 u8 pad11[0x494 - 0x488 - 4];
403 u32 peuiae;
404 u8 pad12[0x4bc - 0x494 - 4];
405 u32 eth_type_prio;
406 u8 pad13[0x4dc - 0x4bc - 4];
407 u32 tqfpc;
408 u32 pttbrc;
409 u32 tqc1;
410 u32 pmtu;
411 u32 pmtbs;
412 u8 pad14[0x60c - 0x4ec - 4];
Albert Aribaudd44265a2010-07-12 22:24:28 +0200413 struct mvgbe_rxcdp rxcdp[7];
414 struct mvgbe_rxdesc *rxcdp7;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530415 u32 rqc;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200416 struct mvgbe_txdesc *tcsdp;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530417 u8 pad15[0x6c0 - 0x684 - 4];
Albert Aribaudd44265a2010-07-12 22:24:28 +0200418 struct mvgbe_txdesc *tcqdp[8];
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530419 u8 pad16[0x700 - 0x6dc - 4];
Albert Aribaudd44265a2010-07-12 22:24:28 +0200420 struct mvgbe_tqx tqx[8];
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530421 u32 pttbc;
422 u8 pad17[0x7a8 - 0x780 - 4];
423 u32 tqxipg0;
424 u32 pad18[3];
425 u32 tqxipg1;
426 u8 pad19[0x7c0 - 0x7b8 - 4];
427 u32 hitkninlopkt;
428 u32 hitkninasyncpkt;
429 u32 lotkninasyncpkt;
430 u32 pad20;
431 u32 ts;
432 u8 pad21[0x3000 - 0x27d0 - 4];
433 u32 pad20_1[32]; /* mib counter registes */
434 u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
435 u32 dfsmt[64];
436 u32 dfomt[64];
437 u32 dfut[4];
438 u8 pad23[0xe20c0 - 0x7360c - 4];
439 u32 pmbus_top_arbiter;
440};
441
442/* structures/enums needed by driver */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200443enum mvgbe_adrwin {
444 MVGBE_WIN0,
445 MVGBE_WIN1,
446 MVGBE_WIN2,
447 MVGBE_WIN3,
448 MVGBE_WIN4,
449 MVGBE_WIN5
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530450};
451
Albert Aribaudd44265a2010-07-12 22:24:28 +0200452enum mvgbe_target {
453 MVGBE_TARGET_DRAM,
454 MVGBE_TARGET_DEV,
455 MVGBE_TARGET_CBS,
456 MVGBE_TARGET_PCI0,
457 MVGBE_TARGET_PCI1
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530458};
459
Albert Aribaudd44265a2010-07-12 22:24:28 +0200460struct mvgbe_winparam {
461 enum mvgbe_adrwin win; /* Window number */
462 enum mvgbe_target target; /* System targets */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530463 u16 attrib; /* BAR attrib. See above macros */
464 u32 base_addr; /* Window base address in u32 form */
465 u32 high_addr; /* Window high address in u32 form */
466 u32 size; /* Size in MBytes. Must be % 64Kbyte. */
467 int enable; /* Enable/disable access to the window. */
468 u16 access_ctrl; /*Access ctrl register. see above macros */
469};
470
Albert Aribaudd44265a2010-07-12 22:24:28 +0200471struct mvgbe_rxdesc {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530472 u32 cmd_sts; /* Descriptor command status */
473 u16 buf_size; /* Buffer size */
474 u16 byte_cnt; /* Descriptor buffer byte count */
475 u8 *buf_ptr; /* Descriptor buffer pointer */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200476 struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530477};
478
Albert Aribaudd44265a2010-07-12 22:24:28 +0200479struct mvgbe_txdesc {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530480 u32 cmd_sts; /* Descriptor command status */
481 u16 l4i_chk; /* CPU provided TCP Checksum */
482 u16 byte_cnt; /* Descriptor buffer byte count */
483 u8 *buf_ptr; /* Descriptor buffer ptr */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200484 struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530485};
486
487/* port device data struct */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200488struct mvgbe_device {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530489 struct eth_device dev;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200490 struct mvgbe_registers *regs;
491 struct mvgbe_txdesc *p_txdesc;
492 struct mvgbe_rxdesc *p_rxdesc;
493 struct mvgbe_rxdesc *p_rxdesc_curr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530494 u8 *p_rxbuf;
Simon Kagstrom477fa632009-08-20 10:14:11 +0200495 u8 *p_aligned_txbuf;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530496};
497
Albert Aribaudd44265a2010-07-12 22:24:28 +0200498#endif /* __MVGBE_H__ */