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Lokesh Vutla853f7f52018-08-27 15:59:09 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
Andreas Dannenberg7202af92019-04-29 12:56:44 -05006#include <dt-bindings/pinctrl/k3.h>
Grygorii Strashko736b6c32019-02-05 17:31:26 +05307#include <dt-bindings/dma/k3-udma.h>
Grygorii Strashko6f2929d2019-07-09 10:30:36 +05308#include <dt-bindings/net/ti-dp83867.h>
Lokesh Vutla853f7f52018-08-27 15:59:09 +05309
10/ {
11 chosen {
12 stdout-path = "serial2:115200n8";
13 };
14
15 aliases {
16 serial2 = &main_uart0;
Grygorii Strashko5195c102019-07-09 10:30:35 +053017 ethernet0 = &cpsw_port1;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053018 };
19};
20
21&cbass_main{
22 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053023
Lokesh Vutla853f7f52018-08-27 15:59:09 +053024 sdhci1: sdhci@04FA0000 {
Faiz Abbas3a1a0df2019-06-11 00:43:31 +053025 compatible = "ti,am654-sdhci-5.1";
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053026 reg = <0x0 0x4FA0000 0x0 0x1000>,
27 <0x0 0x4FB0000 0x0 0x400>;
Faiz Abbasfe0e30c2020-01-16 19:42:18 +053028 clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
29 clock-names = "clk_ahb", "clk_xin";
Lokesh Vutla355be912019-06-07 19:24:47 +053030 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053031 max-frequency = <25000000>;
Faiz Abbasbbcfaad2019-06-11 00:43:36 +053032 ti,otap-del-sel = <0x2>;
33 ti,trm-icp = <0x8>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +053034 };
35
36};
37
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053038&cbass_mcu {
39 u-boot,dm-spl;
Grygorii Strashko736b6c32019-02-05 17:31:26 +053040
41 navss_mcu: navss-mcu {
42 compatible = "simple-bus";
43 #address-cells = <2>;
44 #size-cells = <2>;
45 ranges;
46
47 ti,sci-dev-id = <119>;
48
49 mcu_ringacc: ringacc@2b800000 {
50 compatible = "ti,am654-navss-ringacc";
51 reg = <0x0 0x2b800000 0x0 0x400000>,
52 <0x0 0x2b000000 0x0 0x400000>,
53 <0x0 0x28590000 0x0 0x100>,
54 <0x0 0x2a500000 0x0 0x40000>;
55 reg-names = "rt", "fifos",
56 "proxy_gcfg", "proxy_target";
57 ti,num-rings = <286>;
58 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
59 ti,dma-ring-reset-quirk;
60 ti,sci = <&dmsc>;
61 ti,sci-dev-id = <195>;
62 };
63
64 mcu_udmap: udmap@285c0000 {
65 compatible = "ti,k3-navss-udmap";
66 reg = <0x0 0x285c0000 0x0 0x100>,
67 <0x0 0x2a800000 0x0 0x40000>,
68 <0x0 0x2aa00000 0x0 0x40000>;
69 reg-names = "gcfg", "rchanrt", "tchanrt";
70 #dma-cells = <3>;
71
72 ti,ringacc = <&mcu_ringacc>;
73 ti,psil-base = <0x6000>;
74
75 ti,sci = <&dmsc>;
76 ti,sci-dev-id = <194>;
77
78 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
79 <0x2>; /* TX_CHAN */
80 ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
81 <0x4>; /* RX_CHAN */
82 ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
83 dma-coherent;
84 };
85 };
Grygorii Strashko5195c102019-07-09 10:30:35 +053086
87 mcu_conf: scm_conf@40f00000 {
88 compatible = "syscon";
89 reg = <0x0 0x40f00000 0x0 0x20000>;
90 };
91
92 mcu_cpsw: cpsw_nuss@046000000 {
93 compatible = "ti,am654-cpsw-nuss";
94 #address-cells = <2>;
95 #size-cells = <2>;
96 reg = <0x0 0x46000000 0x0 0x200000>;
97 reg-names = "cpsw_nuss";
98 ranges;
99 dma-coherent;
100 clocks = <&k3_clks 5 10>;
101 clock-names = "fck";
Suman Annadcddf0f2019-07-29 11:13:41 -0500102 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
Grygorii Strashko5195c102019-07-09 10:30:35 +0530103 ti,psil-base = <0x7000>;
104
105 dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
106 <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
107 <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
108 <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
109 <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
110 <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
111 <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
112 <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
113 <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
114 dma-names = "tx0", "tx1", "tx2", "tx3",
115 "tx4", "tx5", "tx6", "tx7",
116 "rx";
117
118 ports {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 host: host@0 {
122 reg = <0>;
123 ti,label = "host";
124 };
125
126 cpsw_port1: port@1 {
127 reg = <1>;
128 ti,mac-only;
129 ti,label = "port1";
130 ti,syscon-efuse = <&mcu_conf 0x200>;
131 };
132 };
133
134 davinci_mdio: mdio {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 bus_freq = <1000000>;
138 };
139
140 ti,psil-config0 {
141 linux,udma-mode = <UDMA_PKT_MODE>;
142 statictr-type = <PSIL_STATIC_TR_NONE>;
143 ti,needs-epib;
144 ti,psd-size = <16>;
145 };
146
147 ti,psil-config1 {
148 linux,udma-mode = <UDMA_PKT_MODE>;
149 statictr-type = <PSIL_STATIC_TR_NONE>;
150 ti,needs-epib;
151 ti,psd-size = <16>;
152 };
153
154 ti,psil-config2 {
155 linux,udma-mode = <UDMA_PKT_MODE>;
156 statictr-type = <PSIL_STATIC_TR_NONE>;
157 ti,needs-epib;
158 ti,psd-size = <16>;
159 };
160
161 ti,psil-config3 {
162 linux,udma-mode = <UDMA_PKT_MODE>;
163 statictr-type = <PSIL_STATIC_TR_NONE>;
164 ti,needs-epib;
165 ti,psd-size = <16>;
166 };
167
168 ti,psil-config4 {
169 linux,udma-mode = <UDMA_PKT_MODE>;
170 statictr-type = <PSIL_STATIC_TR_NONE>;
171 ti,needs-epib;
172 ti,psd-size = <16>;
173 };
174
175 ti,psil-config5 {
176 linux,udma-mode = <UDMA_PKT_MODE>;
177 statictr-type = <PSIL_STATIC_TR_NONE>;
178 ti,needs-epib;
179 ti,psd-size = <16>;
180 };
181
182 ti,psil-config6 {
183 linux,udma-mode = <UDMA_PKT_MODE>;
184 statictr-type = <PSIL_STATIC_TR_NONE>;
185 ti,needs-epib;
186 ti,psd-size = <16>;
187 };
188
189 ti,psil-config7 {
190 linux,udma-mode = <UDMA_PKT_MODE>;
191 statictr-type = <PSIL_STATIC_TR_NONE>;
192 ti,needs-epib;
193 ti,psd-size = <16>;
194 };
195 };
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530196};
197
198&cbass_wakeup {
199 u-boot,dm-spl;
200};
201
202&secure_proxy_main {
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530203 u-boot,dm-spl;
204};
205
206&dmsc {
207 u-boot,dm-spl;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530208 k3_sysreset: sysreset-controller {
209 compatible = "ti,sci-sysreset";
210 u-boot,dm-spl;
211 };
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530212};
213
214&k3_pds {
215 u-boot,dm-spl;
216};
217
218&k3_clks {
219 u-boot,dm-spl;
220};
221
222&k3_reset {
223 u-boot,dm-spl;
224};
225
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500226&wkup_pmx0 {
227 u-boot,dm-spl;
228
229 wkup_i2c0_pins_default {
230 u-boot,dm-spl;
231 };
232};
233
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530234&main_pmx0 {
235 u-boot,dm-spl;
236 main_uart0_pins_default: main_uart0_pins_default {
237 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500238 AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
239 AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
240 AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
241 AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530242 >;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530243 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530244 };
245
246 main_mmc0_pins_default: main_mmc0_pins_default {
247 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500248 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
249 AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
250 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
251 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
252 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
253 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
254 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
255 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
256 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
257 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530258 AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
259 AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530260 >;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530261 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530262 };
263
264 main_mmc1_pins_default: main_mmc1_pins_default {
265 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500266 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
267 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
268 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
269 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
270 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
271 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
272 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
273 AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530274 >;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +0530275 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530276 };
277
278};
279
280&main_pmx1 {
281 u-boot,dm-spl;
282};
283
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530284&wkup_pmx0 {
285 mcu_cpsw_pins_default: mcu_cpsw_pins_default {
286 pinctrl-single,pins = <
287 AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
288 AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
289 AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
290 AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
291 AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
292 AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
293 AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
294 AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
295 AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
296 AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
297 AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
298 AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
299 >;
300 };
301
302 mcu_mdio_pins_default: mcu_mdio1_pins_default {
303 pinctrl-single,pins = <
304 AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
305 AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
306 >;
307 };
308};
309
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530310&main_uart0 {
311 u-boot,dm-spl;
312 pinctrl-names = "default";
313 pinctrl-0 = <&main_uart0_pins_default>;
314 status = "okay";
315};
316
317&sdhci0 {
318 u-boot,dm-spl;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530319};
320
321&sdhci1 {
322 u-boot,dm-spl;
323 status = "okay";
324 pinctrl-names = "default";
325 pinctrl-0 = <&main_mmc1_pins_default>;
326 sdhci-caps-mask = <0x7 0x0>;
Faiz Abbasbbcfaad2019-06-11 00:43:36 +0530327 ti,driver-strength-ohm = <50>;
Lokesh Vutla853f7f52018-08-27 15:59:09 +0530328};
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530329
330&mcu_cpsw {
331 pinctrl-names = "default";
332 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
333};
334
335&davinci_mdio {
336 phy0: ethernet-phy@0 {
337 reg = <0>;
338 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
339 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530340 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
341 };
342};
343
344&cpsw_port1 {
Grygorii Strashko5efb6922019-11-18 23:04:47 +0200345 phy-mode = "rgmii-rxid";
Grygorii Strashko6f2929d2019-07-09 10:30:36 +0530346 phy-handle = <&phy0>;
347};
348
349&mcu_cpsw {
350 reg = <0x0 0x46000000 0x0 0x200000>,
351 <0x0 0x40f00200 0x0 0x2>;
352 reg-names = "cpsw_nuss", "mac_efuse";
353
354 cpsw-phy-sel@40f04040 {
355 compatible = "ti,am654-cpsw-phy-sel";
356 reg= <0x0 0x40f04040 0x0 0x4>;
357 reg-names = "gmii-sel";
358 };
359};
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500360
361&wkup_i2c0 {
362 u-boot,dm-spl;
363};