blob: 8fb4cfa8847f6b2938af4273ae2cf58f41050b32 [file] [log] [blame]
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * Port to AMCC-440SPE Evaluation Board SOP - April 2005
24 */
25
26#include <common.h>
27#include <ppc4xx.h>
28#include <asm/processor.h>
29#include <i2c.h>
30#include "yucca.h"
31
32void fpga_init (void);
33
34void get_sys_info(PPC440_SYS_INFO *board_cfg );
35int compare_to_true(char *str );
36char *remove_l_w_space(char *in_str );
37char *remove_t_w_space(char *in_str );
38int get_console_port(void);
39unsigned long ppcMfcpr(unsigned long cpr_reg);
40unsigned long ppcMfsdr(unsigned long sdr_reg);
41
42#define DEBUG_ENV
43#ifdef DEBUG_ENV
44#define DEBUGF(fmt,args...) printf(fmt ,##args)
45#else
46#define DEBUGF(fmt,args...)
47#endif
48
49#define FALSE 0
50#define TRUE 1
51
52int board_early_init_f (void)
53{
54/*----------------------------------------------------------------------------+
55| Define Boot devices
56+----------------------------------------------------------------------------*/
57#define BOOT_FROM_SMALL_FLASH 0x00
58#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
59#define BOOT_FROM_PCI 0x02
60#define BOOT_DEVICE_UNKNOWN 0x03
61
62/*----------------------------------------------------------------------------+
63| EBC Devices Characteristics
64| Peripheral Bank Access Parameters - EBC_BxAP
65| Peripheral Bank Configuration Register - EBC_BxCR
66+----------------------------------------------------------------------------*/
67
68/*
69 * Small Flash and FRAM
70 * BU Value
71 * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
72 * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
73 * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
74 */
75#define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \
76 EBC_BXAP_TWT_ENCODE(7) | \
77 EBC_BXAP_BCE_DISABLE | \
78 EBC_BXAP_BCT_2TRANS | \
79 EBC_BXAP_CSN_ENCODE(0) | \
80 EBC_BXAP_OEN_ENCODE(0) | \
81 EBC_BXAP_WBN_ENCODE(0) | \
82 EBC_BXAP_WBF_ENCODE(0) | \
83 EBC_BXAP_TH_ENCODE(0) | \
84 EBC_BXAP_RE_DISABLED | \
85 EBC_BXAP_SOR_DELAYED | \
86 EBC_BXAP_BEM_WRITEONLY | \
87 EBC_BXAP_PEN_DISABLED
88
89#define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
90 EBC_BXCR_BS_16MB | \
91 EBC_BXCR_BU_RW | \
92 EBC_BXCR_BW_8BIT
93
94#define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \
95 EBC_BXCR_BS_16MB | \
96 EBC_BXCR_BU_RW | \
97 EBC_BXCR_BW_8BIT
98
99/*
100 * Large Flash and SRAM
101 * BU Value
102 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
103 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
104 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
105*/
106#define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \
107 EBC_BXAP_TWT_ENCODE(7) | \
108 EBC_BXAP_BCE_DISABLE | \
109 EBC_BXAP_BCT_2TRANS | \
110 EBC_BXAP_CSN_ENCODE(0) | \
111 EBC_BXAP_OEN_ENCODE(0) | \
112 EBC_BXAP_WBN_ENCODE(0) | \
113 EBC_BXAP_WBF_ENCODE(0) | \
114 EBC_BXAP_TH_ENCODE(0) | \
115 EBC_BXAP_RE_DISABLED | \
116 EBC_BXAP_SOR_DELAYED | \
117 EBC_BXAP_BEM_WRITEONLY | \
118 EBC_BXAP_PEN_DISABLED
119
120#define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
121 EBC_BXCR_BS_16MB | \
122 EBC_BXCR_BU_RW | \
123 EBC_BXCR_BW_16BIT
124
125#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \
126 EBC_BXCR_BS_16MB | \
127 EBC_BXCR_BU_RW | \
128 EBC_BXCR_BW_16BIT
129
130/*
131 * FPGA
132 * BU value :
133 * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
134 * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
135 */
136#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \
137 EBC_BXAP_TWT_ENCODE(11) | \
138 EBC_BXAP_BCE_DISABLE | \
139 EBC_BXAP_BCT_2TRANS | \
140 EBC_BXAP_CSN_ENCODE(10) | \
141 EBC_BXAP_OEN_ENCODE(1) | \
142 EBC_BXAP_WBN_ENCODE(1) | \
143 EBC_BXAP_WBF_ENCODE(1) | \
144 EBC_BXAP_TH_ENCODE(1) | \
145 EBC_BXAP_RE_DISABLED | \
146 EBC_BXAP_SOR_DELAYED | \
147 EBC_BXAP_BEM_RW | \
148 EBC_BXAP_PEN_DISABLED
149
150#define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \
151 EBC_BXCR_BS_1MB | \
152 EBC_BXCR_BU_RW | \
153 EBC_BXCR_BW_16BIT
154
155 unsigned long mfr;
156 /*
157 * Define Variables for EBC initialization depending on BOOTSTRAP option
158 */
159 unsigned long sdr0_pinstp, sdr0_sdstp1 ;
160 unsigned long bootstrap_settings, ebc_data_width, boot_selection;
161 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
162
163 /*-------------------------------------------------------------------+
164 | Initialize EBC CONFIG -
165 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
166 | default value :
167 | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
168 |
169 +-------------------------------------------------------------------*/
170 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
171 EBC_CFG_PTD_ENABLE |
172 EBC_CFG_RTC_16PERCLK |
173 EBC_CFG_ATC_PREVIOUS |
174 EBC_CFG_DTC_PREVIOUS |
175 EBC_CFG_CTC_PREVIOUS |
176 EBC_CFG_OEO_PREVIOUS |
177 EBC_CFG_EMC_DEFAULT |
178 EBC_CFG_PME_DISABLE |
179 EBC_CFG_PR_16);
180
181 /*-------------------------------------------------------------------+
182 |
183 | PART 1 : Initialize EBC Bank 1
184 | ==============================
185 | Bank1 is always associated to the EPLD.
186 | It has to be initialized prior to other banks settings computation
187 | since some board registers values may be needed to determine the
188 | boot type
189 |
190 +-------------------------------------------------------------------*/
191 mtebc(pb1ap, EBC_BXAP_FPGA);
192 mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
193
194 /*-------------------------------------------------------------------+
195 |
196 | PART 2 : Determine which boot device was selected
197 | =================================================
198 |
199 | Read Pin Strap Register in PPC440SPe
200 | Result can either be :
201 | - Boot strap = boot from EBC 8bits => Small Flash
202 | - Boot strap = boot from PCI
203 | - Boot strap = IIC
204 | In case of boot from IIC, read Serial Device Strap Register1
205 |
206 | Result can either be :
207 | - Boot from EBC - EBC Bus Width = 8bits => Small Flash
208 | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
209 | - Boot from PCI
210 |
211 +-------------------------------------------------------------------*/
212 /* Read Pin Strap Register in PPC440SP */
213 sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
214 bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
215
216 switch (bootstrap_settings) {
217 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
218 /*
219 * Strapping Option A
220 * Boot from EBC - 8 bits , Small Flash
221 */
222 computed_boot_device = BOOT_FROM_SMALL_FLASH;
223 break;
224 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
225 /*
226 * Strappping Option B
227 * Boot from PCI
228 */
229 computed_boot_device = BOOT_FROM_PCI;
230 break;
231 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
232 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
233 /*
234 * Strapping Option C or D
235 * Boot Settings in IIC EEprom address 0x50 or 0x54
236 * Read Serial Device Strap Register1 in PPC440SPe
237 */
238 sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
239 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
240 ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
241
242 switch (boot_selection) {
243 case SDR0_SDSTP1_ERPN_EBC:
244 switch (ebc_data_width) {
245 case SDR0_SDSTP1_EBCW_16_BITS:
246 computed_boot_device =
247 BOOT_FROM_LARGE_FLASH_OR_SRAM;
248 break;
249 case SDR0_SDSTP1_EBCW_8_BITS :
250 computed_boot_device = BOOT_FROM_SMALL_FLASH;
251 break;
252 }
253 break;
254
255 case SDR0_SDSTP1_ERPN_PCI:
256 computed_boot_device = BOOT_FROM_PCI;
257 break;
258 default:
259 /* should not occure */
260 computed_boot_device = BOOT_DEVICE_UNKNOWN;
261 }
262 break;
263 default:
264 /* should not be */
265 computed_boot_device = BOOT_DEVICE_UNKNOWN;
266 break;
267 }
268
269 /*-------------------------------------------------------------------+
270 |
271 | PART 3 : Compute EBC settings depending on selected boot device
272 | ====== ======================================================
273 |
274 | Resulting EBC init will be among following configurations :
275 |
276 | - Boot from EBC 8bits => boot from Small Flash selected
277 | EBC-CS0 = Small Flash
278 | EBC-CS2 = Large Flash and SRAM
279 |
280 | - Boot from EBC 16bits => boot from Large Flash or SRAM
281 | EBC-CS0 = Large Flash or SRAM
282 | EBC-CS2 = Small Flash
283 |
284 | - Boot from PCI
285 | EBC-CS0 = not initialized to avoid address contention
286 | EBC-CS2 = same as boot from Small Flash selected
287 |
288 +-------------------------------------------------------------------*/
289 unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
290 unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
291
292 switch (computed_boot_device) {
293 /*-------------------------------------------------------------------*/
294 case BOOT_FROM_PCI:
295 /*-------------------------------------------------------------------*/
296 /*
297 * By Default CS2 is affected to LARGE Flash
298 * do not initialize SMALL FLASH to avoid address contention
299 * Large Flash
300 */
301 ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
302 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
303 break;
304
305 /*-------------------------------------------------------------------*/
306 case BOOT_FROM_SMALL_FLASH:
307 /*-------------------------------------------------------------------*/
308 ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
309 ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
310
311 /*
312 * Large Flash or SRAM
313 */
314 /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
315 ebc0_cs2_bxap_value = 0x048ff240;
316 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
317 break;
318
319 /*-------------------------------------------------------------------*/
320 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
321 /*-------------------------------------------------------------------*/
322 ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
323 ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
324
325 /* Small flash */
326 ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
327 ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
328 break;
329
330 /*-------------------------------------------------------------------*/
331 default:
332 /*-------------------------------------------------------------------*/
333 /* BOOT_DEVICE_UNKNOWN */
334 break;
335 }
336
337 mtebc(pb0ap, ebc0_cs0_bxap_value);
338 mtebc(pb0cr, ebc0_cs0_bxcr_value);
339 mtebc(pb2ap, ebc0_cs2_bxap_value);
340 mtebc(pb2cr, ebc0_cs2_bxcr_value);
341
342 /*--------------------------------------------------------------------+
343 | Interrupt controller setup for the AMCC 440SPe Evaluation board.
344 +--------------------------------------------------------------------+
345 +---------------------------------------------------------------------+
346 |Interrupt| Source | Pol. | Sensi.| Crit. |
347 +---------+-----------------------------------+-------+-------+-------+
348 | IRQ 00 | UART0 | High | Level | Non |
349 | IRQ 01 | UART1 | High | Level | Non |
350 | IRQ 02 | IIC0 | High | Level | Non |
351 | IRQ 03 | IIC1 | High | Level | Non |
352 | IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
353 | IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
354 | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
355 | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
356 | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
357 | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
358 | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
359 | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
360 | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
361 | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
362 | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
363 | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
364 | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
365 | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
366 | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
367 | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
368 | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
369 | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
370 | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
371 | IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
372 | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
373 | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
374 | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
375 | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
376 | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
377 | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
378 | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
379 | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
380 |----------------------------------------------------------------------
381 | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
382 | IRQ 33 | MAL Serr | High | Level | Non |
383 | IRQ 34 | MAL Txde | High | Level | Non |
384 | IRQ 35 | MAL Rxde | High | Level | Non |
385 | IRQ 36 | DMC CE or DMC UE | High | Level | Non |
386 | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
387 | IRQ 38 | MAL TX EOB | High | Level | Non |
388 | IRQ 39 | MAL RX EOB | High | Level | Non |
389 | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
390 | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
391 | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
392 | IRQ 43 | L2 Cache | Risin | Edge | Non |
393 | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
394 | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
395 | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
396 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
397 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
398 | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
399 | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
400 | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
401 | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
402 | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
403 | IRQ 54 | DMA Error | High | Level | Non |
404 | IRQ 55 | DMA I2O Error | High | Level | Non |
405 | IRQ 56 | Serial ROM | High | Level | Non |
406 | IRQ 57 | PCIX0 Error | High | Edge | Non |
407 | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
408 | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
409 | IRQ 60 | EMAC0 Interrupt | High | Level | Non |
410 | IRQ 61 | EMAC0 Wake-up | High | Level | Non |
411 | IRQ 62 | Reserved | High | Level | Non |
412 | IRQ 63 | XOR | High | Level | Non |
413 |----------------------------------------------------------------------
414 | IRQ 64 | PE0 AL | High | Level | Non |
415 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
416 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
417 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
418 | IRQ 68 | PE0 TCR | High | Level | Non |
419 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
420 | IRQ 70 | PE0 DCR Error | High | Level | Non |
421 | IRQ 71 | Reserved | N/A | N/A | Non |
422 | IRQ 72 | PE1 AL | High | Level | Non |
423 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
424 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
425 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
426 | IRQ 76 | PE1 TCR | High | Level | Non |
427 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
428 | IRQ 78 | PE1 DCR Error | High | Level | Non |
429 | IRQ 79 | Reserved | N/A | N/A | Non |
430 | IRQ 80 | PE2 AL | High | Level | Non |
431 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
432 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
433 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
434 | IRQ 84 | PE2 TCR | High | Level | Non |
435 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
436 | IRQ 86 | PE2 DCR Error | High | Level | Non |
437 | IRQ 87 | Reserved | N/A | N/A | Non |
438 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
439 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
440 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
441 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
442 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
443 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
444 | IRQ 94 | Reserved | N/A | N/A | Non |
445 | IRQ 95 | Reserved | N/A | N/A | Non |
446 |---------------------------------------------------------------------
447 | IRQ 96 | PE0 INTA | High | Level | Non |
448 | IRQ 97 | PE0 INTB | High | Level | Non |
449 | IRQ 98 | PE0 INTC | High | Level | Non |
450 | IRQ 99 | PE0 INTD | High | Level | Non |
451 | IRQ 100 | PE1 INTA | High | Level | Non |
452 | IRQ 101 | PE1 INTB | High | Level | Non |
453 | IRQ 102 | PE1 INTC | High | Level | Non |
454 | IRQ 103 | PE1 INTD | High | Level | Non |
455 | IRQ 104 | PE2 INTA | High | Level | Non |
456 | IRQ 105 | PE2 INTB | High | Level | Non |
457 | IRQ 106 | PE2 INTC | High | Level | Non |
458 | IRQ 107 | PE2 INTD | Risin | Edge | Non |
459 | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
460 | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
461 | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
462 | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
463 | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
464 | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
465 | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
466 | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
467 | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
468 | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
469 | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
470 | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
471 | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
472 | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
473 | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
474 | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
475 | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
476 | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
477 | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
478 | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
479 +---------+-----------------------------------+-------+-------+------*/
480 /*--------------------------------------------------------------------+
481 | Put UICs in PowerPC440SPemode.
482 | Initialise UIC registers. Clear all interrupts. Disable all
483 | interrupts.
484 | Set critical interrupt values. Set interrupt polarities. Set
485 | interrupt trigger levels. Make bit 0 High priority. Clear all
486 | interrupts again.
487 +-------------------------------------------------------------------*/
488 mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
489 mtdcr (uic3er, 0x00000000); /* disable all interrupts */
490 mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical
491 * interrupts */
492 mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */
493 mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
494 mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest
495 * priority */
496 mtdcr (uic3sr, 0x00000000); /* clear all interrupts */
497 mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */
498
499 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
500 mtdcr (uic2er, 0x00000000); /* disable all interrupts */
501 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical
502 * interrupts */
503 mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */
504 mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
505 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest
506 * priority */
507 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
508 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
509
510 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
511 mtdcr (uic1er, 0x00000000); /* disable all interrupts */
512 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical
513 * interrupts */
514 mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
515 mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */
516 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest
517 * priority */
518 mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
519 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
520
521 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
522 mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted
523 * cascade to be checked */
524 mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical
525 * interrupts */
526 mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */
527 mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
528 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest
529 * priority */
530 mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
531 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
532
533 /* SDR0_MFR should be part of Ethernet init */
534 mfsdr (sdr_mfr, mfr);
535 mfr &= ~SDR0_MFR_ECS_MASK;
536 /*mtsdr(sdr_mfr, mfr);*/
537 fpga_init();
538
539 return 0;
540}
541
542int checkboard (void)
543{
544 sys_info_t sysinfo;
545
546 get_sys_info (&sysinfo);
547
548 printf ("Board: AMCC 440SPe Evaluation Board\n");
549 printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
550 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
551 printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
552 printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
553 printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
554 printf ("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
555 printf ("\tDDR: %lu MHz\n", sysinfo.freqDDR / 1000000);
556 return 0;
557}
558
559static long int yucca_probe_for_dimms(void)
560{
561 long int dimm_installed[MAXDIMMS];
562 long int dimm_num, probe_result;
563 long int dimms_found = 0;
564 uchar dimm_addr = IIC0_DIMM0_ADDR;
565
566 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
567 /* check if there is a chip at the dimm address */
568 switch (dimm_num) {
569 case 0:
570 dimm_addr = IIC0_DIMM0_ADDR;
571 break;
572 case 1:
573 dimm_addr = IIC0_DIMM1_ADDR;
574 break;
575 }
576 probe_result = i2c_probe(dimm_addr);
577
578 if (probe_result == 0) {
579 dimm_installed[dimm_num] = TRUE;
580 dimms_found++;
581 debug("DIMM slot %d: DDR2 SDRAM detected\n",dimm_num);
582 } else {
583 dimm_installed[dimm_num] = FALSE;
584 debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
585 }
586 }
587
588 if (dimms_found == 0) {
589 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
590 hang();
591 }
592
593 if (dimm_installed[0] != TRUE) {
594 printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
595 printf(" Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
596 hang();
597 }
598
599 return dimms_found;
600}
601
602/*************************************************************************
603 * init SDRAM controller with fixed value
604 * the initialization values are for 2x MICRON DDR2
605 * PN: MT18HTF6472DY-53EB2
606 * 512MB, DDR2, 533, CL4, ECC, REG
607 ************************************************************************/
608static long int fixed_sdram(void)
609{
610 long int yucca_dimms = 0;
611
612 yucca_dimms = yucca_probe_for_dimms();
613
614 /* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT */
615 mtdcr( 0x10, 0x00000021 );
616 mtdcr( 0x11, 0x84000000 );
617
618 /* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2 */
619 mtdcr( 0x10, 0x00000020 );
620 mtdcr( 0x11, 0x2D122000 );
621
622 /* SET MCIF0_CODT Die Termination On */
623 mtdcr( 0x10, 0x00000026 );
624 if (yucca_dimms == 2)
625 mtdcr( 0x11, 0x2A800021 );
626 else if (yucca_dimms == 1)
627 mtdcr( 0x11, 0x02800021 );
628
629 /* On-Die Termination for Bank 0 */
630 mtdcr( 0x10, 0x00000022 );
631 if (yucca_dimms == 2)
632 mtdcr( 0x11, 0x18000000 );
633 else if (yucca_dimms == 1)
634 mtdcr( 0x11, 0x06000000 );
635
636 /* On-Die Termination for Bank 1 */
637 mtdcr( 0x10, 0x00000023 );
638 if (yucca_dimms == 2)
639 mtdcr( 0x11, 0x18000000 );
640 else if (yucca_dimms == 1)
641 mtdcr( 0x11, 0x01800000 );
642
643 /* On-Die Termination for Bank 2 */
644 mtdcr( 0x10, 0x00000024 );
645 if (yucca_dimms == 2)
646 mtdcr( 0x11, 0x01800000 );
647 else if (yucca_dimms == 1)
648 mtdcr( 0x11, 0x00000000 );
649
650 /* On-Die Termination for Bank 3 */
651 mtdcr( 0x10, 0x00000025 );
652 if (yucca_dimms == 2)
653 mtdcr( 0x11, 0x01800000 );
654 else if (yucca_dimms == 1)
655 mtdcr( 0x11, 0x00000000 );
656
657 /* Refresh Time register (0x30) Refresh every 7.8125uS */
658 mtdcr( 0x10, 0x00000030 );
659 mtdcr( 0x11, 0x08200000 );
660
661 /* SET MCIF0_MMODE CL 4 */
662 mtdcr( 0x10, 0x00000088 );
663 mtdcr( 0x11, 0x00000642 );
664
665 /* MCIF0_MEMODE */
666 mtdcr( 0x10, 0x00000089 );
667 mtdcr( 0x11, 0x00000004 );
668
669 /*SET MCIF0_MB0CF */
670 mtdcr( 0x10, 0x00000040 );
671 mtdcr( 0x11, 0x00000201 );
672
673 /* SET MCIF0_MB1CF */
674 mtdcr( 0x10, 0x00000044 );
675 mtdcr( 0x11, 0x00000201 );
676
677 /* SET MCIF0_MB2CF */
678 mtdcr( 0x10, 0x00000048 );
679 if (yucca_dimms == 2)
680 mtdcr( 0x11, 0x00000201 );
681 else if (yucca_dimms == 1)
682 mtdcr( 0x11, 0x00000000 );
683
684 /* SET MCIF0_MB3CF */
685 mtdcr( 0x10, 0x0000004c );
686 if (yucca_dimms == 2)
687 mtdcr( 0x11, 0x00000201 );
688 else if (yucca_dimms == 1)
689 mtdcr( 0x11, 0x00000000 );
690
691 /* SET MCIF0_INITPLR0 # NOP */
692 mtdcr( 0x10, 0x00000050 );
693 mtdcr( 0x11, 0xB5380000 );
694
695 /* SET MCIF0_INITPLR1 # PRE */
696 mtdcr( 0x10, 0x00000051 );
697 mtdcr( 0x11, 0x82100400 );
698
699 /* SET MCIF0_INITPLR2 # EMR2 */
700 mtdcr( 0x10, 0x00000052 );
701 mtdcr( 0x11, 0x80820000 );
702
703 /* SET MCIF0_INITPLR3 # EMR3 */
704 mtdcr( 0x10, 0x00000053 );
705 mtdcr( 0x11, 0x80830000 );
706
707 /* SET MCIF0_INITPLR4 # EMR DLL ENABLE */
708 mtdcr( 0x10, 0x00000054 );
709 mtdcr( 0x11, 0x80810000 );
710
711 /* SET MCIF0_INITPLR5 # MR DLL RESET */
712 mtdcr( 0x10, 0x00000055 );
713 mtdcr( 0x11, 0x80800542 );
714
715 /* SET MCIF0_INITPLR6 # PRE */
716 mtdcr( 0x10, 0x00000056 );
717 mtdcr( 0x11, 0x82100400 );
718
719 /* SET MCIF0_INITPLR7 # Refresh */
720 mtdcr( 0x10, 0x00000057 );
721 mtdcr( 0x11, 0x8A080000 );
722
723 /* SET MCIF0_INITPLR8 # Refresh */
724 mtdcr( 0x10, 0x00000058 );
725 mtdcr( 0x11, 0x8A080000 );
726
727 /* SET MCIF0_INITPLR9 # Refresh */
728 mtdcr( 0x10, 0x00000059 );
729 mtdcr( 0x11, 0x8A080000 );
730
731 /* SET MCIF0_INITPLR10 # Refresh */
732 mtdcr( 0x10, 0x0000005A );
733 mtdcr( 0x11, 0x8A080000 );
734
735 /* SET MCIF0_INITPLR11 # MR */
736 mtdcr( 0x10, 0x0000005B );
737 mtdcr( 0x11, 0x80800442 );
738
739 /* SET MCIF0_INITPLR12 # EMR OCD Default*/
740 mtdcr( 0x10, 0x0000005C );
741 mtdcr( 0x11, 0x80810380 );
742
743 /* SET MCIF0_INITPLR13 # EMR OCD Exit */
744 mtdcr( 0x10, 0x0000005D );
745 mtdcr( 0x11, 0x80810000 );
746
747 /* 0x80: Adv Addr clock by 180 deg */
748 mtdcr( 0x10, 0x00000080 );
749 mtdcr( 0x11, 0x80000000 );
750
751 /* 0x21: Exit self refresh, set DC_EN */
752 mtdcr( 0x10, 0x00000021 );
753 mtdcr( 0x11, 0x28000000 );
754
755 /* 0x81: Write DQS Adv 90 + Fractional DQS Delay */
756 mtdcr( 0x10, 0x00000081 );
757 mtdcr( 0x11, 0x80000800 );
758
759 /* MCIF0_SDTR1 */
760 mtdcr( 0x10, 0x00000085 );
761 mtdcr( 0x11, 0x80201000 );
762
763 /* MCIF0_SDTR2 */
764 mtdcr( 0x10, 0x00000086 );
765 mtdcr( 0x11, 0x42103242 );
766
767 /* MCIF0_SDTR3 */
768 mtdcr( 0x10, 0x00000087 );
769 mtdcr( 0x11, 0x0C100D14 );
770
771 /* SET MQ0_B0BAS base addr 00000000 / 256MB */
772 mtdcr( 0x40, 0x0000F800 );
773
774 /* SET MQ0_B1BAS base addr 10000000 / 256MB */
775 mtdcr( 0x41, 0x0400F800 );
776
777 /* SET MQ0_B2BAS base addr 20000000 / 256MB */
778 if (yucca_dimms == 2)
779 mtdcr( 0x42, 0x0800F800 );
780 else if (yucca_dimms == 1)
781 mtdcr( 0x42, 0x00000000 );
782
783 /* SET MQ0_B3BAS base addr 30000000 / 256MB */
784 if (yucca_dimms == 2)
785 mtdcr( 0x43, 0x0C00F800 );
786 else if (yucca_dimms == 1)
787 mtdcr( 0x43, 0x00000000 );
788
789 /* SDRAM_RQDC */
790 mtdcr( 0x10, 0x00000070 );
791 mtdcr( 0x11, 0x8000003F );
792
793 /* SDRAM_RDCC */
794 mtdcr( 0x10, 0x00000078 );
795 mtdcr( 0x11, 0x80000000 );
796
797 /* SDRAM_RFDC */
798 mtdcr( 0x10, 0x00000074 );
799 mtdcr( 0x11, 0x00000220 );
800
801 return (yucca_dimms * 512) << 20;
802}
803
804long int initdram (int board_type)
805{
806 long dram_size = 0;
807
808 dram_size = fixed_sdram();
809
810 return dram_size;
811}
812
813#if defined(CFG_DRAM_TEST)
814int testdram (void)
815{
816 uint *pstart = (uint *) 0x00000000;
817 uint *pend = (uint *) 0x08000000;
818 uint *p;
819
820 for (p = pstart; p < pend; p++)
821 *p = 0xaaaaaaaa;
822
823 for (p = pstart; p < pend; p++) {
824 if (*p != 0xaaaaaaaa) {
825 printf ("SDRAM test fails at: %08x\n", (uint) p);
826 return 1;
827 }
828 }
829
830 for (p = pstart; p < pend; p++)
831 *p = 0x55555555;
832
833 for (p = pstart; p < pend; p++) {
834 if (*p != 0x55555555) {
835 printf ("SDRAM test fails at: %08x\n", (uint) p);
836 return 1;
837 }
838 }
839 return 0;
840}
841#endif
842
843/*************************************************************************
844 * pci_pre_init
845 *
846 * This routine is called just prior to registering the hose and gives
847 * the board the opportunity to check things. Returning a value of zero
848 * indicates that things are bad & PCI initialization should be aborted.
849 *
850 * Different boards may wish to customize the pci controller structure
851 * (add regions, override default access routines, etc) or perform
852 * certain pre-initialization actions.
853 *
854 ************************************************************************/
855#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
856int pci_pre_init(struct pci_controller * hose )
857{
858 unsigned long strap;
859
860 /*-------------------------------------------------------------------+
861 * The yucca board is always configured as the host & requires the
862 * PCI arbiter to be enabled.
863 *-------------------------------------------------------------------*/
864 mfsdr(sdr_sdstp1, strap);
865 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
866 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
867 return 0;
868 }
869
870 return 1;
871}
872#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
873
874/*************************************************************************
875 * pci_target_init
876 *
877 * The bootstrap configuration provides default settings for the pci
878 * inbound map (PIM). But the bootstrap config choices are limited and
879 * may not be sufficient for a given board.
880 *
881 ************************************************************************/
882#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
883void pci_target_init(struct pci_controller * hose )
884{
885 DECLARE_GLOBAL_DATA_PTR;
886
887 /*-------------------------------------------------------------------+
888 * Disable everything
889 *-------------------------------------------------------------------*/
890 out32r( PCIX0_PIM0SA, 0 ); /* disable */
891 out32r( PCIX0_PIM1SA, 0 ); /* disable */
892 out32r( PCIX0_PIM2SA, 0 ); /* disable */
893 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
894
895 /*-------------------------------------------------------------------+
896 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
897 * strapping options to not support sizes such as 128/256 MB.
898 *-------------------------------------------------------------------*/
899 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
900 out32r( PCIX0_PIM0LAH, 0 );
901 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
902 out32r( PCIX0_BAR0, 0 );
903
904 /*-------------------------------------------------------------------+
905 * Program the board's subsystem id/vendor id
906 *-------------------------------------------------------------------*/
907 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
908 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
909
910 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
911}
912#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
913
914/*************************************************************************
915 * is_pci_host
916 *
917 * This routine is called to determine if a pci scan should be
918 * performed. With various hardware environments (especially cPCI and
919 * PPMC) it's insufficient to depend on the state of the arbiter enable
920 * bit in the strap register, or generic host/adapter assumptions.
921 *
922 * Rather than hard-code a bad assumption in the general 440 code, the
923 * 440 pci code requires the board to decide at runtime.
924 *
925 * Return 0 for adapter mode, non-zero for host (monarch) mode.
926 *
927 *
928 ************************************************************************/
929#if defined(CONFIG_PCI)
930int is_pci_host(struct pci_controller *hose)
931{
932 /* The yucca board is always configured as host. */
933 return 1;
934}
935#endif /* defined(CONFIG_PCI) */
936
937int misc_init_f (void)
938{
939 uint reg;
940#if defined(CONFIG_STRESS)
941 uint i ;
942 uint disp;
943#endif
944
945 out16(FPGA_REG10, (in16(FPGA_REG10) &
946 ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
947 FPGA_REG10_10MHZ_ENABLE |
948 FPGA_REG10_100MHZ_ENABLE |
949 FPGA_REG10_GIGABIT_ENABLE |
950 FPGA_REG10_FULL_DUPLEX );
951
952 udelay(10000); /* wait 10ms */
953
954 out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
955
956 /* minimal init for PCIe */
957 /* pci express 0 Endpoint Mode */
958 mfsdr(SDR0_PE0DLPSET, reg);
959 reg &= (~0x00400000);
960 mtsdr(SDR0_PE0DLPSET, reg);
961 /* pci express 1 Rootpoint Mode */
962 mfsdr(SDR0_PE1DLPSET, reg);
963 reg |= 0x00400000;
964 mtsdr(SDR0_PE1DLPSET, reg);
965 /* pci express 2 Rootpoint Mode */
966 mfsdr(SDR0_PE2DLPSET, reg);
967 reg |= 0x00400000;
968 mtsdr(SDR0_PE2DLPSET, reg);
969
970 out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
971 ~FPGA_REG1C_PE0_ROOTPOINT &
972 ~FPGA_REG1C_PE1_ENDPOINT &
973 ~FPGA_REG1C_PE2_ENDPOINT));
974
975#if defined(CONFIG_STRESS)
976 /*
977 * all this setting done by linux only needed by stress an charac. test
978 * procedure
979 * PCIe 1 Rootpoint PCIe2 Endpoint
980 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
981 * Power Level
982 */
983 for (i = 0, disp = 0; i < 8; i++, disp += 3) {
984 mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
985 reg |= 0x33000000;
986 mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
987 }
988
989 /*
990 * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
991 * Power Level
992 */
993 for (i = 0, disp = 0; i < 4; i++, disp += 3) {
994 mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
995 reg |= 0x33000000;
996 mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
997 }
998
999 /*
1000 * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
1001 * Power Level
1002 */
1003 for (i = 0, disp = 0; i < 4; i++, disp += 3) {
1004 mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
1005 reg |= 0x33000000;
1006 mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
1007 }
1008
1009 reg = 0x21242222;
1010 mtsdr(SDR0_PE2UTLSET1, reg);
1011 reg = 0x11000000;
1012 mtsdr(SDR0_PE2UTLSET2, reg);
1013 /* pci express 1 Endpoint Mode */
1014 reg = 0x00004000;
1015 mtsdr(SDR0_PE2DLPSET, reg);
1016
1017 mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
1018#endif
1019 return 0;
1020}
1021
1022void fpga_init(void)
1023{
1024 /*
1025 * by default sdram access is disabled by fpga
1026 */
1027 out16(FPGA_REG10, (in16 (FPGA_REG10) |
1028 FPGA_REG10_SDRAM_ENABLE |
1029 FPGA_REG10_ENABLE_DISPLAY ));
1030
1031 return;
1032}
1033
1034#ifdef CONFIG_POST
1035/*
1036 * Returns 1 if keys pressed to start the power-on long-running tests
1037 * Called from board_init_f().
1038 */
1039int post_hotkeys_pressed(void)
1040{
1041 return (ctrlc());
1042}
1043#endif
1044
1045/*---------------------------------------------------------------------------+
1046 | onboard_pci_arbiter_selected => from EPLD
1047 +---------------------------------------------------------------------------*/
1048int onboard_pci_arbiter_selected(int core_pci)
1049{
1050#if 0
1051 unsigned long onboard_pci_arbiter_sel;
1052
1053 onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
1054
1055 if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
1056 return (BOARD_OPTION_SELECTED);
1057 else
1058#endif
1059 return (BOARD_OPTION_NOT_SELECTED);
1060}
1061
1062/*---------------------------------------------------------------------------+
1063 | ppcMfcpr.
1064 +---------------------------------------------------------------------------*/
1065unsigned long ppcMfcpr(unsigned long cpr_reg)
1066{
1067 unsigned long msr;
1068 unsigned long cpr_cfgaddr_temp;
1069 unsigned long cpr_value;
1070
1071 msr = (mfmsr () & ~(MSR_EE));
1072 cpr_cfgaddr_temp = mfdcr(CPR0_CFGADDR);
1073 mtdcr(CPR0_CFGADDR, cpr_reg);
1074 cpr_value = mfdcr(CPR0_CFGDATA);
1075 mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
1076 mtmsr(msr);
1077
1078 return (cpr_value);
1079}
1080
1081/*----------------------------------------------------------------------------+
1082| Indirect Access of the System DCR's (SDR)
1083| ppcMfsdr
1084+----------------------------------------------------------------------------*/
1085unsigned long ppcMfsdr(unsigned long sdr_reg)
1086{
1087 unsigned long msr;
1088 unsigned long sdr_cfgaddr_temp;
1089 unsigned long sdr_value;
1090
1091 msr = (mfmsr () & ~(MSR_EE));
1092 sdr_cfgaddr_temp = mfdcr(SDR0_CFGADDR);
1093 mtdcr(SDR0_CFGADDR, sdr_reg);
1094 sdr_value = mfdcr(SDR0_CFGDATA);
1095 mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);
1096 mtmsr(msr);
1097
1098 return (sdr_value);
1099}
1100