Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 44728b8b3d669b06f494aa6a4fbbb8b469ad059b / arch / riscv / cpu / start.S
  1. f6cb427 riscv: update fix_rela_dyn by Marcus Comstedt · 5 years ago
  2. c7e1eff riscv: support SPL stack and global data relocation by Lukas Auer · 5 years ago
  3. 8c59f20 riscv: add SPL support by Lukas Auer · 5 years ago
  4. fbfd92b riscv: add run mode configuration for SPL by Lukas Auer · 5 years ago
  5. 4d2583d riscv: Access CSRs using CSR numbers by Bin Meng · 5 years ago
  6. f9281b8 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · 6 years ago
  7. bdce389 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · 6 years ago
  8. 8ac39e2 riscv: hang if relocation of secondary harts fails by Lukas Auer · 6 years ago
  9. e043240 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · 6 years ago
  10. 3dea63c riscv: add support for multi-hart systems by Lukas Auer · 6 years ago
  11. 1446b26 riscv: save hart ID in register tp instead of s0 by Lukas Auer · 6 years ago
  12. 2503ccc riscv: delay initialization of caches and debug UART by Lukas Auer · 6 years ago
  13. 51ab457 riscv: Save boot hart id to the global data by Bin Meng · 6 years ago
  14. 4b3f5ed riscv: Move trap handler codes to mtrap.S by Bin Meng · 6 years ago
  15. 48cbf62 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · 6 years ago
  16. d2db2a8 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · 6 years ago
  17. 52923c6 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · 6 years ago
  18. 5d8b2e7 riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · 6 years ago
  19. 31f9058 riscv: do not blindly modify the mstatus CSR by Lukas Auer · 6 years ago
  20. 8bfa231 riscv: remove unused labels in start.S by Lukas Auer · 6 years ago
  21. c95cafd Drop CONFIG_INIT_CRITICAL by Bin Meng · 6 years ago
  22. 2a23ac6 riscv: align mtvec on a 4-byte boundary by Lukas Auer · 6 years ago
  23. c55309c riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · 6 years ago
  24. b5369c5 riscv: Make start.S available for all targets by Bin Meng · 6 years ago[Renamed from arch/riscv/cpu/ax25/start.S]
  25. 6f4dd62 riscv: cpu: nx25: Rename as ax25 by Rick Chen · 7 years ago[Renamed from arch/riscv/cpu/nx25/start.S]
  26. 83d290c SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 7 years ago
  27. d58717e riscv: ae250: Support DT provided by the board at runtime by Rick Chen · 7 years ago
  28. e8e3959 riscv: cpu: Add nx25 to support RISC-V by Rick Chen · 7 years ago