- c1b8819 riscv: ae350: dts: Update L2 cache compatible string by Yu Chien Peter Lin · 1 year, 10 months ago
- a5dfa3b riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · 2 years, 1 month ago
- 77eae0e riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config by Bin Meng · 3 years, 6 months ago
- 048aff6 riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit by Bin Meng · 3 years, 6 months ago
- f050dd2 riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes by Bin Meng · 3 years, 6 months ago
- 5c267e0 riscv: ae350: dts: Remove the unnecessary space in bootargs by Bin Meng · 3 years, 6 months ago
- 2ff6b79 riscv: ae350: dts: Add SPDX license header by Bin Meng · 3 years, 6 months ago
- cc269e1 riscv: ae350: Switch to use binman to generate u-boot.itb by Bin Meng · 3 years, 7 months ago
- cca8b1e riscv: dts: Add #address-cells and #size-cells in nor node by Rick Chen · 5 years ago
- f05b656 riscv: dts: Support four cores SMP by Rick Chen · 5 years ago
- cf6ee11 riscv: dts: move out AE350 L2 node from cpus node by Rick Chen · 5 years ago
- ffd4c7c dts: switch spi-flash to jedec, spi-nor compatible by Neil Armstrong · 6 years ago
- a1ce531 riscv: dts: ae350 support SMP by Rick Chen · 6 years ago
- bae2d72 riscv: dts: Add ae350_32.dts for RV32I by Rick Chen · 6 years ago