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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 83083febf55679ee0fc68ba55e9af43add277b58 / arch / riscv / cpu
  1. 90ae281 riscv: add option to wait for ack from secondary harts in smp functions by Lukas Auer · 5 years ago
  2. 444c464 riscv: Fix clear bss loop in the start-up code by Rick Chen · 5 years ago
  3. 8ba595b riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL by Rick Chen · 5 years ago
  4. ca06444 riscv: ax25: add SPL support by Rick Chen · 5 years ago
  5. 67c4e9f common: Move board_get_usable_ram_top() out of common.h by Simon Glass · 5 years ago
  6. 36bf446 common: Move enable/disable_interrupts out of common.h by Simon Glass · 5 years ago
  7. 1eb69ae common: Move ARM cache operations out of common.h by Simon Glass · 5 years ago
  8. 9edefc2 common: Move some cache and MMU functions out of common.h by Simon Glass · 5 years ago
  9. 61ce84b riscv: cache: use CCTL to flush d-cache by Rick Chen · 5 years ago
  10. 7045ed9 riscv: cache: Flush L2 cache before jump to linux by Rick Chen · 5 years ago
  11. a8323d1 riscv: ax25: add imply v5l2 cache controller by Rick Chen · 5 years ago
  12. f6cb427 riscv: update fix_rela_dyn by Marcus Comstedt · 5 years ago
  13. c7e1eff riscv: support SPL stack and global data relocation by Lukas Auer · 5 years ago
  14. 8c59f20 riscv: add SPL support by Lukas Auer · 5 years ago
  15. fbfd92b riscv: add run mode configuration for SPL by Lukas Auer · 5 years ago
  16. 4d2583d riscv: Access CSRs using CSR numbers by Bin Meng · 5 years ago
  17. 1001502 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · 6 years ago
  18. f9281b8 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · 6 years ago
  19. bdce389 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · 6 years ago
  20. dda00ae riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · 6 years ago
  21. 8848474 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · 6 years ago
  22. 8ac39e2 riscv: hang if relocation of secondary harts fails by Lukas Auer · 6 years ago
  23. e043240 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · 6 years ago
  24. 3dea63c riscv: add support for multi-hart systems by Lukas Auer · 6 years ago
  25. 1446b26 riscv: save hart ID in register tp instead of s0 by Lukas Auer · 6 years ago
  26. 2503ccc riscv: delay initialization of caches and debug UART by Lukas Auer · 6 years ago
  27. 26f4fd1 riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems by Anup Patel · 6 years ago
  28. fdff1f9 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · 6 years ago
  29. c905665 riscv: move the AX25-specific implementation of flush_dcache_all by Lukas Auer · 6 years ago
  30. 51ab457 riscv: Save boot hart id to the global data by Bin Meng · 6 years ago
  31. 10753ef riscv: Return to previous privilege level after trap handling by Bin Meng · 6 years ago
  32. 496262c riscv: Fix context restore before returning from trap handler by Bin Meng · 6 years ago
  33. 4b3f5ed riscv: Move trap handler codes to mtrap.S by Bin Meng · 6 years ago
  34. 485e822 riscv: Do some basic architecture level cpu initialization by Bin Meng · 6 years ago
  35. aef59e5 riscv: Update supports_extension() to use desc from cpu driver by Bin Meng · 6 years ago
  36. 3c276b2 riscv: Remove non-DM version of print_cpuinfo() by Bin Meng · 6 years ago
  37. 39cad5b riscv: Probe cpus during boot by Bin Meng · 6 years ago
  38. 84304d4 riscv: qemu: Add platform-specific Kconfig options by Bin Meng · 6 years ago
  39. 44fe795 riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · 6 years ago
  40. 27dc2c1 riscv: qemu: Create a simple-bus driver for the soc node by Bin Meng · 6 years ago
  41. 48cbf62 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · 6 years ago
  42. d2db2a8 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · 6 years ago
  43. 52923c6 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · 6 years ago
  44. 5d8b2e7 riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · 6 years ago
  45. 31f9058 riscv: do not blindly modify the mstatus CSR by Lukas Auer · 6 years ago
  46. 8bfa231 riscv: remove unused labels in start.S by Lukas Auer · 6 years ago
  47. c95cafd Drop CONFIG_INIT_CRITICAL by Bin Meng · 6 years ago
  48. 2a23ac6 riscv: align mtvec on a 4-byte boundary by Lukas Auer · 6 years ago
  49. c55309c riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · 6 years ago
  50. b984ddc riscv: Move do_reset() to a common place by Bin Meng · 6 years ago
  51. 510e379 riscv: Add QEMU virt board support by Bin Meng · 6 years ago
  52. b5369c5 riscv: Make start.S available for all targets by Bin Meng · 6 years ago
  53. 2fab2e9 riscv: Add a helper routine to print CPU information by Bin Meng · 6 years ago
  54. 3d60156 riscv: Fix coding style issues in the linker script by Bin Meng · 6 years ago
  55. dfb828e riscv: Move the linker script to the CPU root directory by Bin Meng · 6 years ago
  56. 122347f riscv: Include bss subsections in linker script by Alexander Graf · 6 years ago
  57. 7e21fbc efi_loader: Rename sections to allow for implicit data by Alexander Graf · 6 years ago
  58. 6f4dd62 riscv: cpu: nx25: Rename as ax25 by Rick Chen · 7 years ago
  59. 6836adb efi_loader: Enable RISC-V support by Rick Chen · 7 years ago
  60. 83d290c SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 7 years ago
  61. d58717e riscv: ae250: Support DT provided by the board at runtime by Rick Chen · 7 years ago
  62. e8e3959 riscv: cpu: Add nx25 to support RISC-V by Rick Chen · 7 years ago