1. a6d7e8c riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · 3 years, 8 months ago
  2. 529d5f9 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · 3 years, 10 months ago
  3. c33efaf riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · 4 years, 3 months ago
  4. 8c59f20 riscv: add SPL support by Lukas Auer · 5 years ago
  5. fbfd92b riscv: add run mode configuration for SPL by Lukas Auer · 5 years ago
  6. fdff1f9 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · 6 years ago[Renamed (91%) from arch/riscv/cpu/qemu/Kconfig]
  7. b3820ba Merge tag 'efi-2019-04-rc3' of https://github.com/xypron2/u-boot by Tom Rini · 6 years ago