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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ea0211b61f133b6cf9cad690436f60f067c3439a / arch / mips / include / asm / mipsregs.h
  1. 65d297a MIPS: fix iand optimize setup of CP0 registers by Daniel Schwierzeck · 9 years ago
  2. 31d36f7 MIPS: Hang if run on a secondary CPU by Paul Burton · 8 years ago
  3. 4baa0ab MIPS: L2 cache support by Paul Burton · 8 years ago
  4. 4f9226b MIPS: Preserve Config implementation-defined bits by Paul Burton · 8 years ago
  5. a3ab2ae MIPS: sync processor and register definitions with linux-4.4 by Daniel Schwierzeck · 9 years ago
  6. 73a4152 mips: Use unsigned int when reading c0 registers by Chris Packham · 9 years ago
  7. fa476f7 mips32: detect L1 cache sizes if they're not defined by Paul Burton · 11 years ago
  8. 819833a Move architecture-specific includes to arch/$ARCH/include/asm by Peter Tyser · 15 years ago[Renamed from include/asm-mips/mipsregs.h]
  9. e2ad842 [MIPS] <asm/mipsregs.h>: Update coprocessor register access macros by Shinya Kuribayashi · 16 years ago
  10. 1a3adac [MIPS] <asm/mipsregs.h>: Update register / bit field definitions by Shinya Kuribayashi · 16 years ago
  11. bf462ae [MIPS] <asm/mipsregs.h>: CodinygStyle cleanups by Shinya Kuribayashi · 16 years ago
  12. 53677ef Big white-space cleanup. by Wolfgang Denk · 16 years ago
  13. 5da627a * Patch by Steven Scholz, 10 Oct 2003 - Add support for Altera FPGA ACEX1K by wdenk · 21 years ago
  14. 8bde7f7 * Code cleanup: by wdenk · 21 years ago
  15. 6069ff2 * Add support for 16 MB flash configuration of TRAB board by wdenk · 22 years ago