1. 9b7aac7 clk: zynq: Add dummy clock enable function by Michal Simek · 3 years, 10 months ago
  2. 8b85dfc dm: Avoid accessing seq directly by Simon Glass · 4 years ago
  3. 8a8d24b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · 4 years ago
  4. d1998a9 dm: treewide: Rename ofdata_to_platdata() to of_to_plat() by Simon Glass · 4 years ago
  5. c69cda2 dm: treewide: Rename dev_get_platdata() to dev_get_plat() by Simon Glass · 4 years ago
  6. caa4daa dm: treewide: Rename 'platdata' variables to just 'plat' by Simon Glass · 4 years ago
  7. 41575d8 dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · 4 years ago
  8. 5028358 watchdog: versal: Add support for Xilinx window watchdog by Ashok Reddy Soma · 4 years, 9 months ago