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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / fd55792e143f7ec46c5e70a8683183163d8c6878 / arch / riscv / cpu / andesv5 / Kconfig
  1. fd55792 riscv: andesv5: Set default cache line size to 64-bytes by Yu Chien Peter Lin · 9 months ago
  2. 8a0d5f2 riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode by Yu Chien Peter Lin · 1 year, 4 months ago
  3. 8900e2b riscv: Rename Andes cpu and board names by Leo Yu-Chi Liang · 1 year, 11 months ago[Renamed from arch/riscv/cpu/ax25/Kconfig]
  4. 487c211 configs: ae350: Enable v5l2 cache for AE350 platforms in SPL by Yu Chien Peter Lin · 2 years ago
  5. 55ca747 riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" by Leo Yu-Chi Liang · 2 years ago
  6. faac9de Prepare v2023.04-rc2 by Tom Rini · 1 year, 11 months ago