blob: 3982896cb3282abad57b95beed10c01b5aee33ef [file] [log] [blame]
Stefan Roesec157d8e2005-08-01 16:41:48 +02001/*
Stefan Roese5a5958b2007-10-15 11:29:33 +02002 * (C) Copyright 2006-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
Stefan Roesec157d8e2005-08-01 16:41:48 +02004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
Stefan Roese84286382005-08-11 18:03:14 +020025#include <ppc4xx.h>
Stefan Roesec157d8e2005-08-01 16:41:48 +020026#include <asm/processor.h>
Stefan Roese5a5958b2007-10-15 11:29:33 +020027#include <asm/io.h>
Stefan Roesec157d8e2005-08-01 16:41:48 +020028#include <spd_sdram.h>
Ira Snyder4adb3022008-04-29 11:18:54 -070029#include <libfdt.h>
30#include <fdt_support.h>
Stefan Roesec157d8e2005-08-01 16:41:48 +020031
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
Stefan Roese84286382005-08-11 18:03:14 +020035
Stefan Roesec157d8e2005-08-01 16:41:48 +020036int board_early_init_f(void)
37{
38 register uint reg;
39
40 /*--------------------------------------------------------------------
41 * Setup the external bus controller/chip selects
42 *-------------------------------------------------------------------*/
43 mtdcr(ebccfga, xbcfg);
44 reg = mfdcr(ebccfgd);
45 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
46
Stefan Roesec157d8e2005-08-01 16:41:48 +020047 /*--------------------------------------------------------------------
Stefan Roesec157d8e2005-08-01 16:41:48 +020048 * Setup the GPIO pins
49 *-------------------------------------------------------------------*/
50 /*CPLD cs */
Stefan Roese81a31702005-12-15 09:43:12 +010051 /*setup Address lines for flash size 64Meg. */
52 out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
53 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
54 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
Stefan Roesec157d8e2005-08-01 16:41:48 +020055
56 /*setup emac */
57 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
58 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
59 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
60 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
61 out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
62
63 /*UART1 */
64 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
65 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
66 out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
67
Stefan Roesee1902902005-10-28 12:21:06 +020068 /* external interrupts IRQ0...3 */
Wolfgang Denkb9b24802006-05-30 17:45:30 +020069 out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
70 out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
Stefan Roesee1902902005-10-28 12:21:06 +020071 out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
72
Stefan Roese700200c2007-01-30 17:04:19 +010073#ifdef CONFIG_440EP
Stefan Roesec157d8e2005-08-01 16:41:48 +020074 /*setup USB 2.0 */
75 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
76 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
77 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
78 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
79 out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
Stefan Roese700200c2007-01-30 17:04:19 +010080#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +020081
82 /*--------------------------------------------------------------------
Stefan Roeseef04a0a2005-11-03 08:31:33 +010083 * Setup the interrupt controller polarities, triggers, etc.
84 *-------------------------------------------------------------------*/
85 mtdcr(uic0sr, 0xffffffff); /* clear all */
86 mtdcr(uic0er, 0x00000000); /* disable all */
87 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
88 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
89 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
90 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
91 mtdcr(uic0sr, 0xffffffff); /* clear all */
92
93 mtdcr(uic1sr, 0xffffffff); /* clear all */
94 mtdcr(uic1er, 0x00000000); /* disable all */
95 mtdcr(uic1cr, 0x00000000); /* all non-critical */
96 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
97 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
98 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
99 mtdcr(uic1sr, 0xffffffff); /* clear all */
100
101 /*--------------------------------------------------------------------
Stefan Roesec157d8e2005-08-01 16:41:48 +0200102 * Setup other serial configuration
103 *-------------------------------------------------------------------*/
104 mfsdr(sdr_pci0, reg);
105 mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
106 mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
107 mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
108
109 /*clear tmrclk divisor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200111
112 /*enable ethernet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200114
Stefan Roese700200c2007-01-30 17:04:19 +0100115#ifdef CONFIG_440EP
Stefan Roesec157d8e2005-08-01 16:41:48 +0200116 /*enable usb 1.1 fs device and remove usb 2.0 reset */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
Stefan Roese700200c2007-01-30 17:04:19 +0100118#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200119
120 /*get rid of flash write protect */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200122
123 return 0;
124}
125
Stefan Roese84286382005-08-11 18:03:14 +0200126int misc_init_r (void)
127{
Stefan Roese84286382005-08-11 18:03:14 +0200128 uint pbcr;
129 int size_val = 0;
130
131 /* Re-do sizing to get full correct info */
132 mtdcr(ebccfga, pb0cr);
133 pbcr = mfdcr(ebccfgd);
134 switch (gd->bd->bi_flashsize) {
135 case 1 << 20:
136 size_val = 0;
137 break;
138 case 2 << 20:
139 size_val = 1;
140 break;
141 case 4 << 20:
142 size_val = 2;
143 break;
144 case 8 << 20:
145 size_val = 3;
146 break;
147 case 16 << 20:
148 size_val = 4;
149 break;
150 case 32 << 20:
151 size_val = 5;
152 break;
153 case 64 << 20:
154 size_val = 6;
155 break;
156 case 128 << 20:
157 size_val = 7;
158 break;
159 }
160 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
161 mtdcr(ebccfga, pb0cr);
162 mtdcr(ebccfgd, pbcr);
163
Stefan Roesef190c112005-11-05 15:50:16 +0100164 /* adjust flash start and offset */
165 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
166 gd->bd->bi_flashoffset = 0;
167
Stefan Roese84286382005-08-11 18:03:14 +0200168 /* Monitor protection ON by default */
169 (void)flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 -CONFIG_SYS_MONITOR_LEN,
Stefan Roese84286382005-08-11 18:03:14 +0200171 0xffffffff,
172 &flash_info[0]);
173
174 return 0;
175}
176
Stefan Roesec157d8e2005-08-01 16:41:48 +0200177int checkboard(void)
178{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100179 char *s = getenv("serial#");
Stefan Roese36adff32007-01-13 07:59:19 +0100180 u8 rev;
181 u8 val;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200182
Stefan Roese700200c2007-01-30 17:04:19 +0100183#ifdef CONFIG_440EP
Stefan Roese93b17ec2005-10-03 15:27:50 +0200184 printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
Stefan Roese700200c2007-01-30 17:04:19 +0100185#else
186 printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
187#endif
Stefan Roese36adff32007-01-13 07:59:19 +0100188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
190 val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
Stefan Roese36adff32007-01-13 07:59:19 +0100191 printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
192
Stefan Roese93b17ec2005-10-03 15:27:50 +0200193 if (s != NULL) {
194 puts(", serial# ");
195 puts(s);
196 }
197 putc('\n');
198
Stefan Roesec157d8e2005-08-01 16:41:48 +0200199 return (0);
200}
201
202/*************************************************************************
Stefan Roesebbeff302008-06-02 17:37:28 +0200203 * initdram -- doesn't use serial presence detect.
Stefan Roesec157d8e2005-08-01 16:41:48 +0200204 *
205 * Assumes: 256 MB, ECC, non-registered
206 * PLB @ 133 MHz
207 *
208 ************************************************************************/
Stefan Roese81a31702005-12-15 09:43:12 +0100209#define NUM_TRIES 64
210#define NUM_READS 10
211
212void sdram_tr1_set(int ram_address, int* tr1_value)
213{
214 int i;
215 int j, k;
216 volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
217 int first_good = -1, last_bad = 0x1ff;
218
219 unsigned long test[NUM_TRIES] = {
220 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
221 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
222 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
223 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
224 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
225 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
226 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
227 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
228 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
229 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
230 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
231 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
232 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
233 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
234 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
235 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
236
237 /* go through all possible SDRAM0_TR1[RDCT] values */
238 for (i=0; i<=0x1ff; i++) {
239 /* set the current value for TR1 */
240 mtsdram(mem_tr1, (0x80800800 | i));
241
242 /* write values */
243 for (j=0; j<NUM_TRIES; j++) {
244 ram_pointer[j] = test[j];
245
246 /* clear any cache at ram location */
247 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
248 }
249
250 /* read values back */
251 for (j=0; j<NUM_TRIES; j++) {
252 for (k=0; k<NUM_READS; k++) {
253 /* clear any cache at ram location */
254 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
255
256 if (ram_pointer[j] != test[j])
257 break;
258 }
259
260 /* read error */
261 if (k != NUM_READS) {
262 break;
263 }
264 }
265
266 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
267 if (j == NUM_TRIES) {
268 if (first_good == -1)
269 first_good = i; /* found beginning of window */
270 } else { /* bad read */
271 /* if we have not had a good read then don't care */
272 if(first_good != -1) {
273 /* first failure after a good read */
274 last_bad = i-1;
275 break;
276 }
277 }
278 }
279
280 /* return the current value for TR1 */
281 *tr1_value = (first_good + last_bad) / 2;
282}
283
Becky Bruce9973e3c2008-06-09 16:03:40 -0500284phys_size_t initdram(int board)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200285{
286 register uint reg;
Stefan Roese81a31702005-12-15 09:43:12 +0100287 int tr1_bank1, tr1_bank2;
Stefan Roesec157d8e2005-08-01 16:41:48 +0200288
289 /*--------------------------------------------------------------------
290 * Setup some default
291 *------------------------------------------------------------------*/
292 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
293 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
294 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
295 mtsdram(mem_clktr, 0x40000000); /* ?? */
296 mtsdram(mem_wddctr, 0x40000000); /* ?? */
297
298 /*clear this first, if the DDR is enabled by a debugger
Stefan Roese81a31702005-12-15 09:43:12 +0100299 then you can not make changes. */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200300 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
301
302 /*--------------------------------------------------------------------
303 * Setup for board-specific specific mem
304 *------------------------------------------------------------------*/
305 /*
306 * Following for CAS Latency = 2.5 @ 133 MHz PLB
307 */
308 mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
309 mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
310
311 mtsdram(mem_tr0, 0x410a4012); /* ?? */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200312 mtsdram(mem_rtr, 0x04080000); /* ?? */
313 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
Stefan Roesea2c95a72006-07-28 18:34:58 +0200314 mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200315 udelay(400); /* Delay 200 usecs (min) */
316
317 /*--------------------------------------------------------------------
318 * Enable the controller, then wait for DCEN to complete
319 *------------------------------------------------------------------*/
Stefan Roesea2c95a72006-07-28 18:34:58 +0200320 mtsdram(mem_cfg0, 0x80000000); /* Enable */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200321
322 for (;;) {
323 mfsdram(mem_mcsts, reg);
324 if (reg & 0x80000000)
325 break;
326 }
Stefan Roese81a31702005-12-15 09:43:12 +0100327
328 sdram_tr1_set(0x00000000, &tr1_bank1);
329 sdram_tr1_set(0x08000000, &tr1_bank2);
Stefan Roesebbeff302008-06-02 17:37:28 +0200330 mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
Stefan Roesec157d8e2005-08-01 16:41:48 +0200331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332 return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200333}
334
Stefan Roesec157d8e2005-08-01 16:41:48 +0200335/*************************************************************************
336 * pci_pre_init
337 *
338 * This routine is called just prior to registering the hose and gives
339 * the board the opportunity to check things. Returning a value of zero
340 * indicates that things are bad & PCI initialization should be aborted.
341 *
342 * Different boards may wish to customize the pci controller structure
343 * (add regions, override default access routines, etc) or perform
344 * certain pre-initialization actions.
345 *
346 ************************************************************************/
Stefan Roese466fff12007-06-25 15:57:39 +0200347#if defined(CONFIG_PCI)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200348int pci_pre_init(struct pci_controller *hose)
349{
Stefan Roesec157d8e2005-08-01 16:41:48 +0200350 unsigned long addr;
351
Stefan Roesec157d8e2005-08-01 16:41:48 +0200352 /*-------------------------------------------------------------------------+
353 | Set priority for all PLB3 devices to 0.
354 | Set PLB3 arbiter to fair mode.
355 +-------------------------------------------------------------------------*/
356 mfsdr(sdr_amp1, addr);
357 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
358 addr = mfdcr(plb3_acr);
359 mtdcr(plb3_acr, addr | 0x80000000);
360
361 /*-------------------------------------------------------------------------+
362 | Set priority for all PLB4 devices to 0.
363 +-------------------------------------------------------------------------*/
364 mfsdr(sdr_amp0, addr);
365 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
366 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
367 mtdcr(plb4_acr, addr);
368
369 /*-------------------------------------------------------------------------+
370 | Set Nebula PLB4 arbiter to fair mode.
371 +-------------------------------------------------------------------------*/
372 /* Segment0 */
373 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
374 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
375 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
376 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
377 mtdcr(plb0_acr, addr);
378
379 /* Segment1 */
380 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
381 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
382 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
383 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
384 mtdcr(plb1_acr, addr);
385
386 return 1;
387}
Stefan Roese466fff12007-06-25 15:57:39 +0200388#endif /* defined(CONFIG_PCI) */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200389
390/*************************************************************************
391 * pci_target_init
392 *
393 * The bootstrap configuration provides default settings for the pci
394 * inbound map (PIM). But the bootstrap config choices are limited and
395 * may not be sufficient for a given board.
396 *
397 ************************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200399void pci_target_init(struct pci_controller *hose)
400{
401 /*--------------------------------------------------------------------------+
402 * Set up Direct MMIO registers
403 *--------------------------------------------------------------------------*/
404 /*--------------------------------------------------------------------------+
405 | PowerPC440 EP PCI Master configuration.
406 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
407 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
408 | Use byte reversed out routines to handle endianess.
409 | Make this region non-prefetchable.
410 +--------------------------------------------------------------------------*/
411 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412 out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
413 out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200414 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
415 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
416
417 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418 out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
419 out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200420 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
421 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
422
423 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
424 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
425 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
426 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
427
428 /*--------------------------------------------------------------------------+
429 * Set up Configuration registers
430 *--------------------------------------------------------------------------*/
431
432 /* Program the board's subsystem id/vendor id */
433 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434 CONFIG_SYS_PCI_SUBSYS_VENDORID);
435 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200436
437 /* Configure command register as bus master */
438 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
439
440 /* 240nS PCI clock */
441 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
442
443 /* No error reporting */
444 pci_write_config_word(0, PCI_ERREN, 0);
445
446 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
447
448}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200450
451/*************************************************************************
452 * pci_master_init
453 *
454 ************************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200456void pci_master_init(struct pci_controller *hose)
457{
458 unsigned short temp_short;
459
460 /*--------------------------------------------------------------------------+
461 | Write the PowerPC440 EP PCI Configuration regs.
462 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
463 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
464 +--------------------------------------------------------------------------*/
465 pci_read_config_word(0, PCI_COMMAND, &temp_short);
466 pci_write_config_word(0, PCI_COMMAND,
467 temp_short | PCI_COMMAND_MASTER |
468 PCI_COMMAND_MEMORY);
469}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200471
472/*************************************************************************
473 * is_pci_host
474 *
475 * This routine is called to determine if a pci scan should be
476 * performed. With various hardware environments (especially cPCI and
477 * PPMC) it's insufficient to depend on the state of the arbiter enable
478 * bit in the strap register, or generic host/adapter assumptions.
479 *
480 * Rather than hard-code a bad assumption in the general 440 code, the
481 * 440 pci code requires the board to decide at runtime.
482 *
483 * Return 0 for adapter mode, non-zero for host (monarch) mode.
484 *
485 *
486 ************************************************************************/
487#if defined(CONFIG_PCI)
488int is_pci_host(struct pci_controller *hose)
489{
490 /* Bamboo is always configured as host. */
491 return (1);
492}
493#endif /* defined(CONFIG_PCI) */
494
495/*************************************************************************
496 * hw_watchdog_reset
497 *
498 * This routine is called to reset (keep alive) the watchdog timer
499 *
500 ************************************************************************/
501#if defined(CONFIG_HW_WATCHDOG)
502void hw_watchdog_reset(void)
503{
504
505}
506#endif
Stefan Roesef3443862006-10-07 11:30:52 +0200507
508void board_reset(void)
509{
510 /* give reset to BCSR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
Stefan Roesef3443862006-10-07 11:30:52 +0200512}