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wdenk1eaeb582004-06-08 00:22:43 +00001/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenk1eaeb582004-06-08 00:22:43 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
wdenk1eaeb582004-06-08 00:22:43 +000014 * High Level Configuration Options
15 * (easy to change)
16 */
17#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
18#define CONFIG_OMAP 1 /* in a TI OMAP core */
19#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */
20#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */
21
Stefan Roese6080a0e2006-05-10 10:55:16 +020022#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
23#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
24
wdenk1eaeb582004-06-08 00:22:43 +000025/* input clock of PLL */
26/* the OMAP5912 OSK has 12MHz input clock */
27#define CONFIG_SYS_CLK_FREQ 12000000
28
wdenk1eaeb582004-06-08 00:22:43 +000029#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
30#define CONFIG_SETUP_MEMORY_TAGS 1
Stefan Roese6080a0e2006-05-10 10:55:16 +020031#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */
wdenk1eaeb582004-06-08 00:22:43 +000032
33/*
34 * Size of malloc() pool
35 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk1eaeb582004-06-08 00:22:43 +000037
38/*
39 * Hardware drivers
40 */
41/*
42*/
Nishanth Menonac6b3622009-10-16 00:06:37 -050043#define CONFIG_LAN91C96
wdenk1eaeb582004-06-08 00:22:43 +000044#define CONFIG_LAN91C96_BASE 0x04800300
45#define CONFIG_LAN91C96_EXT_PHY
46
47/*
48 * NS16550 Configuration
49 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_NS16550
51#define CONFIG_SYS_NS16550_SERIAL
52#define CONFIG_SYS_NS16550_REG_SIZE (-4)
53#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
54#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
wdenk1eaeb582004-06-08 00:22:43 +000055 on helen */
56
57/*
58 * select serial console configuration
59 */
60#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */
61
62/* allow to overwrite serial and ethaddr */
63#define CONFIG_ENV_OVERWRITE
64#define CONFIG_CONS_INDEX 1
65#define CONFIG_BAUDRATE 115200
Jon Loeligera5cb2302007-07-04 22:33:13 -050066
67/*
68 * Command line configuration.
69 */
70#include <config_cmd_default.h>
71
72#define CONFIG_CMD_DHCP
73
74
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050075/*
76 * BOOTP options
77 */
78#define CONFIG_BOOTP_SUBNETMASK
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81#define CONFIG_BOOTP_BOOTPATH
82
wdenk1eaeb582004-06-08 00:22:43 +000083
wdenk1eaeb582004-06-08 00:22:43 +000084#include <configs/omap1510.h>
85
86#define CONFIG_BOOTDELAY 3
87#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \
88 root=/dev/nfs rw nfsroot=157.87.82.48:\
89 /home/mwd/myfs/target ip=dhcp"
90#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */
91#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */
92#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
93#define CONFIG_BOOTFILE "uImage" /* file to load */
94
Jon Loeligera5cb2302007-07-04 22:33:13 -050095#if defined(CONFIG_CMD_KGDB)
wdenk1eaeb582004-06-08 00:22:43 +000096#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
wdenk1eaeb582004-06-08 00:22:43 +000097#endif
98
99/*
100 * Miscellaneous configurable options
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_LONGHELP /* undef to save memory */
103#define CONFIG_SYS_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */
104#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk1eaeb582004-06-08 00:22:43 +0000105/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
107#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
108#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk1eaeb582004-06-08 00:22:43 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
111#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenk1eaeb582004-06-08 00:22:43 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
wdenk1eaeb582004-06-08 00:22:43 +0000114
115/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
116 * DPLL1. This time is further subdivided by a local divisor.
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
Ladislav Michl81472d82009-03-30 18:58:41 +0200119#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
wdenk1eaeb582004-06-08 00:22:43 +0000120
121/*-----------------------------------------------------------------------
wdenk1eaeb582004-06-08 00:22:43 +0000122 * Physical Memory Map
123 */
124#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200125#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
wdenk1eaeb582004-06-08 00:22:43 +0000126#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
127
Stefan Roese6080a0e2006-05-10 10:55:16 +0200128#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
129#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
wdenk1eaeb582004-06-08 00:22:43 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
Stefan Roese6080a0e2006-05-10 10:55:16 +0200132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
wdenk1eaeb582004-06-08 00:22:43 +0000134
Aneesh V0f33ef92011-06-09 08:54:48 -0400135#define PHYS_SRAM 0x20000000
136
wdenk1eaeb582004-06-08 00:22:43 +0000137/*-----------------------------------------------------------------------
Stefan Roese6080a0e2006-05-10 10:55:16 +0200138 * FLASH driver setup
wdenk1eaeb582004-06-08 00:22:43 +0000139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200141#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
Stefan Roese6080a0e2006-05-10 10:55:16 +0200144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenk1eaeb582004-06-08 00:22:43 +0000146#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
150#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk1eaeb582004-06-08 00:22:43 +0000153
154/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
156#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk1eaeb582004-06-08 00:22:43 +0000157
Stefan Roese6080a0e2006-05-10 10:55:16 +0200158/*-----------------------------------------------------------------------
159 * FLASH and environment organization
160 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200161#define CONFIG_ENV_IS_IN_FLASH 1
Stefan Roese6080a0e2006-05-10 10:55:16 +0200162/* addr of environment */
Jon Hunter54ef1f62013-04-09 16:41:32 -0500163#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
Stefan Roese6080a0e2006-05-10 10:55:16 +0200164
Jon Hunter54ef1f62013-04-09 16:41:32 -0500165#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
166#define CONFIG_ENV_OFFSET 0x40000 /* environment starts here */
wdenk1eaeb582004-06-08 00:22:43 +0000167
Jon Hunter2a309f32013-04-09 16:41:31 -0500168#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
169#define CONFIG_SYS_INIT_RAM_ADDR PHYS_SRAM
170#define CONFIG_SYS_INIT_RAM_SIZE (250 * 1024)
171#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
172 CONFIG_SYS_INIT_RAM_SIZE)
Aneesh V0f33ef92011-06-09 08:54:48 -0400173
wdenk1eaeb582004-06-08 00:22:43 +0000174#endif /* __CONFIG_H */