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wdenk1eaeb582004-06-08 00:22:43 +00001/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
wdenk1eaeb582004-06-08 00:22:43 +000030 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
34#define CONFIG_OMAP 1 /* in a TI OMAP core */
35#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */
36#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */
37
Stefan Roese6080a0e2006-05-10 10:55:16 +020038#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
39#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
40
wdenk1eaeb582004-06-08 00:22:43 +000041/* input clock of PLL */
42/* the OMAP5912 OSK has 12MHz input clock */
43#define CONFIG_SYS_CLK_FREQ 12000000
44
45#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
46
47#define CONFIG_MISC_INIT_R
48
49#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
50#define CONFIG_SETUP_MEMORY_TAGS 1
Stefan Roese6080a0e2006-05-10 10:55:16 +020051#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */
wdenk1eaeb582004-06-08 00:22:43 +000052
53/*
54 * Size of malloc() pool
55 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk1eaeb582004-06-08 00:22:43 +000057
58/*
59 * Hardware drivers
60 */
61/*
62*/
Nishanth Menonac6b3622009-10-16 00:06:37 -050063#define CONFIG_NET_MULTI
64#define CONFIG_LAN91C96
wdenk1eaeb582004-06-08 00:22:43 +000065#define CONFIG_LAN91C96_BASE 0x04800300
66#define CONFIG_LAN91C96_EXT_PHY
67
68/*
69 * NS16550 Configuration
70 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_NS16550
72#define CONFIG_SYS_NS16550_SERIAL
73#define CONFIG_SYS_NS16550_REG_SIZE (-4)
74#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
75#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
wdenk1eaeb582004-06-08 00:22:43 +000076 on helen */
77
78/*
79 * select serial console configuration
80 */
81#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */
82
83/* allow to overwrite serial and ethaddr */
84#define CONFIG_ENV_OVERWRITE
85#define CONFIG_CONS_INDEX 1
86#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk1eaeb582004-06-08 00:22:43 +000088
Jon Loeligera5cb2302007-07-04 22:33:13 -050089
90/*
91 * Command line configuration.
92 */
93#include <config_cmd_default.h>
94
95#define CONFIG_CMD_DHCP
96
97
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050098/*
99 * BOOTP options
100 */
101#define CONFIG_BOOTP_SUBNETMASK
102#define CONFIG_BOOTP_GATEWAY
103#define CONFIG_BOOTP_HOSTNAME
104#define CONFIG_BOOTP_BOOTPATH
105
wdenk1eaeb582004-06-08 00:22:43 +0000106
wdenk1eaeb582004-06-08 00:22:43 +0000107#include <configs/omap1510.h>
108
109#define CONFIG_BOOTDELAY 3
110#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \
111 root=/dev/nfs rw nfsroot=157.87.82.48:\
112 /home/mwd/myfs/target ip=dhcp"
113#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */
114#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */
115#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
116#define CONFIG_BOOTFILE "uImage" /* file to load */
117
Jon Loeligera5cb2302007-07-04 22:33:13 -0500118#if defined(CONFIG_CMD_KGDB)
wdenk1eaeb582004-06-08 00:22:43 +0000119#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
120#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
121#endif
122
123/*
124 * Miscellaneous configurable options
125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_LONGHELP /* undef to save memory */
127#define CONFIG_SYS_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */
128#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk1eaeb582004-06-08 00:22:43 +0000129/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
131#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
132#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk1eaeb582004-06-08 00:22:43 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
135#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenk1eaeb582004-06-08 00:22:43 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
wdenk1eaeb582004-06-08 00:22:43 +0000138
139/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
140 * DPLL1. This time is further subdivided by a local divisor.
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
Ladislav Michl81472d82009-03-30 18:58:41 +0200143#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
144#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
wdenk1eaeb582004-06-08 00:22:43 +0000145
146/*-----------------------------------------------------------------------
147 * Stack sizes
148 *
149 * The stack sizes are set up in start.S using the settings below
150 */
151#define CONFIG_STACKSIZE (128*1024) /* regular stack */
152#ifdef CONFIG_USE_IRQ
153#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
154#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
155#endif
156
157/*-----------------------------------------------------------------------
158 * Physical Memory Map
159 */
160#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200161#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
wdenk1eaeb582004-06-08 00:22:43 +0000162#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
163
Stefan Roese6080a0e2006-05-10 10:55:16 +0200164#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
165#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
wdenk1eaeb582004-06-08 00:22:43 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
Stefan Roese6080a0e2006-05-10 10:55:16 +0200168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
wdenk1eaeb582004-06-08 00:22:43 +0000170
Aneesh V0f33ef92011-06-09 08:54:48 -0400171#define PHYS_SRAM 0x20000000
172
wdenk1eaeb582004-06-08 00:22:43 +0000173/*-----------------------------------------------------------------------
Stefan Roese6080a0e2006-05-10 10:55:16 +0200174 * FLASH driver setup
wdenk1eaeb582004-06-08 00:22:43 +0000175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200177#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
Stefan Roese6080a0e2006-05-10 10:55:16 +0200180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenk1eaeb582004-06-08 00:22:43 +0000182#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
186#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
Stefan Roese6080a0e2006-05-10 10:55:16 +0200187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk1eaeb582004-06-08 00:22:43 +0000189
190/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
192#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk1eaeb582004-06-08 00:22:43 +0000193
Stefan Roese6080a0e2006-05-10 10:55:16 +0200194/*-----------------------------------------------------------------------
195 * FLASH and environment organization
196 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200197#define CONFIG_ENV_IS_IN_FLASH 1
Stefan Roese6080a0e2006-05-10 10:55:16 +0200198/* addr of environment */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
Stefan Roese6080a0e2006-05-10 10:55:16 +0200200
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200201#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
202#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
wdenk1eaeb582004-06-08 00:22:43 +0000203
Aneesh V0f33ef92011-06-09 08:54:48 -0400204#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
205#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
206
wdenk1eaeb582004-06-08 00:22:43 +0000207#endif /* __CONFIG_H */