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wdenk281e00a2004-08-01 22:48:16 +00001/*
2 * Copyright (C) 2003 ETC s.r.o.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenk281e00a2004-08-01 22:48:16 +00005 * Written by Peter Figuli <peposh@etc.sk>, 2003.
6 *
7 * 2003/13/06 Initial MP10 Support copied from wepep250
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
14#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
15#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
wdenk281e00a2004-08-01 22:48:16 +000016
Jean-Christophe PLAGNIOL-VILLARDd3e55d02009-03-30 18:58:38 +020017#define CONFIG_IMX_SERIAL
wdenk281e00a2004-08-01 22:48:16 +000018#define CONFIG_IMX_SERIAL1
19/*
20 * Select serial console configuration
21 */
22
wdenk281e00a2004-08-01 22:48:16 +000023/*
Jon Loeliger079a1362007-07-10 10:12:10 -050024 * BOOTP options
25 */
26#define CONFIG_BOOTP_BOOTFILESIZE
27#define CONFIG_BOOTP_BOOTPATH
28#define CONFIG_BOOTP_GATEWAY
29#define CONFIG_BOOTP_HOSTNAME
30
Jon Loeliger079a1362007-07-10 10:12:10 -050031/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050032 * Command line configuration.
wdenk281e00a2004-08-01 22:48:16 +000033 */
Jon Loeliger46da1e92007-07-04 22:33:30 -050034#include <config_cmd_default.h>
wdenk281e00a2004-08-01 22:48:16 +000035
Jon Loeliger46da1e92007-07-04 22:33:30 -050036#define CONFIG_CMD_NET
37#define CONFIG_CMD_PING
38#define CONFIG_CMD_DHCP
39
Jon Loeliger46da1e92007-07-04 22:33:30 -050040#undef CONFIG_CMD_CONSOLE
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020041#undef CONFIG_CMD_LOADS
42#undef CONFIG_CMD_SOURCE
Jon Loeliger46da1e92007-07-04 22:33:30 -050043
wdenk281e00a2004-08-01 22:48:16 +000044/*
45 * Boot options. Setting delay to -1 stops autostart count down.
46 * NOTE: Sending parameters to kernel depends on kernel version and
47 * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
48 * parameters at all! Do not get confused by them so.
49 */
50#define CONFIG_BOOTDELAY -1
51#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
52#define CONFIG_BOOTCOMMAND "bootm 10040000"
53#define CONFIG_SHOW_BOOT_PROGRESS
54#define CONFIG_ETHADDR 80:81:82:83:84:85
55#define CONFIG_NETMASK 255.255.255.0
56#define CONFIG_IPADDR 10.10.10.9
57#define CONFIG_SERVERIP 10.10.10.10
58
59/*
60 * General options for u-boot. Modify to save memory foot print
61 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_LONGHELP /* undef saves memory */
63#define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */
64#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
65#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
66#define CONFIG_SYS_MAXARGS 16 /* max command args */
67#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
wdenk281e00a2004-08-01 22:48:16 +000068
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
70#define CONFIG_SYS_MEMTEST_END 0x08F00000
wdenk281e00a2004-08-01 22:48:16 +000071
Marek Vasutf90aea22013-11-04 20:50:21 +010072#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
wdenk281e00a2004-08-01 22:48:16 +000074
wdenk281e00a2004-08-01 22:48:16 +000075#define CONFIG_BAUDRATE 115200
76/*
77 * Definitions related to passing arguments to kernel.
78 */
79#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
80#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
81#define CONFIG_INITRD_TAG 1 /* send initrd params */
wdenk281e00a2004-08-01 22:48:16 +000082
wdenk281e00a2004-08-01 22:48:16 +000083/*
84 * Malloc pool need to host env + 128 Kb reserve for other allocations.
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
wdenk281e00a2004-08-01 22:48:16 +000087
wdenk281e00a2004-08-01 22:48:16 +000088/* SDRAM Setup Values
890x910a8300 Precharge Command CAS 3
900x910a8200 Precharge Command CAS 2
91
920xa10a8300 AutoRefresh Command CAS 3
930xa10a8200 Set AutoRefresh Command CAS 2 */
94
95#define PRECHARGE_CMD 0x910a8200
96#define AUTOREFRESH_CMD 0xa10a8200
wdenk281e00a2004-08-01 22:48:16 +000097
98/*
99 * SDRAM Memory Map
100 */
101/* SH FIXME */
102#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
103#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
104#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
105
Torsten Koschorrek386393c2011-07-14 23:16:51 +0000106#define CONFIG_SYS_TEXT_BASE 0x10000000
107
108#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1
109#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
110
wdenk281e00a2004-08-01 22:48:16 +0000111/*
wdenk281e00a2004-08-01 22:48:16 +0000112 * Configuration for FLASH memory for the Synertronixx board
113 */
114
115/* #define SCB9328_FLASH_32M */
116
117/* 32MB */
118#ifdef SCB9328_FLASH_32M
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
120#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
wdenk281e00a2004-08-01 22:48:16 +0000121#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
122#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
123#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
124#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
125#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
126#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
127#else
128
129/* 16MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
131#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
wdenk281e00a2004-08-01 22:48:16 +0000132#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
133#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
134#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
135#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
136#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
137#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
138#endif /* SCB9328_FLASH_32M */
139
140/* This should be defined if CFI FLASH device is present. Actually benefit
141 is not so clear to me. In other words we can provide more informations
142 to user, but this expects more complex flash handling we do not provide
143 now.*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#undef CONFIG_SYS_FLASH_CFI
wdenk281e00a2004-08-01 22:48:16 +0000145
Marek Vasutf90aea22013-11-04 20:50:21 +0100146#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */
147#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */
wdenk281e00a2004-08-01 22:48:16 +0000148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE
wdenk281e00a2004-08-01 22:48:16 +0000150
151/*
152 * This is setting for JFFS2 support in u-boot.
153 * Right now there is no gain for user, but later on booting kernel might be
154 * possible. Consider using XIP kernel running from flash to save RAM
155 * footprint.
Jon Loeliger079a1362007-07-10 10:12:10 -0500156 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
wdenk281e00a2004-08-01 22:48:16 +0000157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_JFFS2_FIRST_BANK 0
159#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
160#define CONFIG_SYS_JFFS2_NUM_BANKS 1
wdenk281e00a2004-08-01 22:48:16 +0000161
162/*
163 * Environment setup. Definitions of monitor location and size with
164 * definition of environment setup ends up in 2 possibilities.
165 * 1. Embeded environment - in u-boot code is space for environment
166 * 2. Environment is read from predefined sector of flash
167 * Right now we support 2. possiblity, but expecting no env placed
168 * on mentioned address right now. This also needs to provide whole
169 * sector for it - for us 256Kb is really waste of memory. U-boot uses
170 * default env. and until kernel parameters could be sent to kernel
171 * env. has no sense to us.
172 */
173
174/* Setup for PA23 which is Reset Default PA23 but has to become
175 CS5 */
176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_GPR_A_VAL 0x00800000
178#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe
wdenk281e00a2004-08-01 22:48:16 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_MONITOR_BASE 0x10000000
181#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200182#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200183#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
184#define CONFIG_ENV_SIZE 0x20000
wdenk281e00a2004-08-01 22:48:16 +0000185
186#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
187
188/*
189 * CSxU_VAL:
190 * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
191 * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
192 *
193 * CSxL_VAL:
194 * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
195 * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
196 */
197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_CS0U_VAL 0x000F2000
199#define CONFIG_SYS_CS0L_VAL 0x11110d01
200#define CONFIG_SYS_CS1U_VAL 0x000F0a00
201#define CONFIG_SYS_CS1L_VAL 0x11110601
202#define CONFIG_SYS_CS2U_VAL 0x0
203#define CONFIG_SYS_CS2L_VAL 0x0
wdenk281e00a2004-08-01 22:48:16 +0000204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
206#define CONFIG_SYS_CS3L_VAL 0x00000303
wdenk281e00a2004-08-01 22:48:16 +0000207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_CS4U_VAL 0x000F0a00
209#define CONFIG_SYS_CS4L_VAL 0x11110301
wdenk281e00a2004-08-01 22:48:16 +0000210
211/* CNC == 3 too long
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
wdenk281e00a2004-08-01 22:48:16 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214/* #define CONFIG_SYS_CS5U_VAL 0x00008400
wdenk281e00a2004-08-01 22:48:16 +0000215 mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
216 kaum langsamer ist */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217/* #define CONFIG_SYS_CS5U_VAL 0x00009400
218 #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
wdenk281e00a2004-08-01 22:48:16 +0000219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_CS5U_VAL 0x00008400
221#define CONFIG_SYS_CS5L_VAL 0x00000D03
wdenk281e00a2004-08-01 22:48:16 +0000222
223#define CONFIG_DRIVER_DM9000 1
wdenk281e00a2004-08-01 22:48:16 +0000224#define CONFIG_DM9000_BASE 0x16000000
225#define DM9000_IO CONFIG_DM9000_BASE
226#define DM9000_DATA (CONFIG_DM9000_BASE+4)
wdenk281e00a2004-08-01 22:48:16 +0000227
228/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
229 f_ref=16,777MHz
230
231 0x002a141f: 191,9944MHz
232 0x040b2007: 144MHz
233 0x042a141f: 96MHz
234 0x0811140d: 64MHz
235 0x040e200e: 150MHz
236 0x00321431: 200MHz
237
238 0x08001800: 64MHz mit 16er Quarz
239 0x04001800: 96MHz mit 16er Quarz
240 0x04002400: 144MHz mit 16er Quarz
241
242 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
243 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
244
245#define CPU200
246
247#ifdef CPU200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_MPCTL0_VAL 0x00321431
wdenk281e00a2004-08-01 22:48:16 +0000249#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
wdenk281e00a2004-08-01 22:48:16 +0000251#endif
252
253/* #define BUS64 */
254#define BUS72
255
256#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_SPCTL0_VAL 0x04002400
wdenk281e00a2004-08-01 22:48:16 +0000258#endif
259
260#ifdef BUS96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_SPCTL0_VAL 0x04001800
wdenk281e00a2004-08-01 22:48:16 +0000262#endif
263
264#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_SPCTL0_VAL 0x08001800
wdenk281e00a2004-08-01 22:48:16 +0000266#endif
267
268/* Das ist der BCLK Divider, der aus der System PLL
269 BCLK und HCLK erzeugt:
270 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
271 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
272 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
273 0x2f001003 : 192MHz/5=38,4MHz
274 0x2f000003 : 64MHz/1
275 Bit 22: SPLL Restart
276 Bit 21: MPLL Restart */
277
278#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_CSCR_VAL 0x2f030003
wdenk281e00a2004-08-01 22:48:16 +0000280#endif
281
282#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_CSCR_VAL 0x2f030403
wdenk281e00a2004-08-01 22:48:16 +0000284#endif
285
286/*
287 * Well this has to be defined, but on the other hand it is used differently
288 * one may expect. For instance loadb command do not cares :-)
289 * So advice is - do not relay on this...
290 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_LOAD_ADDR 0x08400000
wdenk281e00a2004-08-01 22:48:16 +0000292
293#define MHZ16QUARZINUSE
294
295#ifdef MHZ16QUARZINUSE
296#define CONFIG_SYSPLL_CLK_FREQ 16000000
297#else
298#define CONFIG_SYSPLL_CLK_FREQ 16780000
299#endif
300
301#define CONFIG_SYS_CLK_FREQ 16780000
302
303/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_FMCR_VAL 0x00000001
wdenk281e00a2004-08-01 22:48:16 +0000305
306/* Bit[0:3] contain PERCLK1DIV for UART 1
307 0x000b00b ->b<- -> 192MHz/12=16MHz
308 0x000b00b ->8<- -> 144MHz/09=16MHz
309 0x000b00b ->3<- -> 64MHz/4=16MHz */
310
311#ifdef BUS96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_PCDR_VAL 0x000b00b5
wdenk281e00a2004-08-01 22:48:16 +0000313#endif
314
315#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_PCDR_VAL 0x000b00b3
wdenk281e00a2004-08-01 22:48:16 +0000317#endif
318
319#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PCDR_VAL 0x000b00b8
wdenk281e00a2004-08-01 22:48:16 +0000321#endif
322
323#endif /* __CONFIG_H */