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wdenk281e00a2004-08-01 22:48:16 +00001/*
2 * Copyright (C) 2003 ETC s.r.o.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 * Written by Peter Figuli <peposh@etc.sk>, 2003.
20 *
21 * 2003/13/06 Initial MP10 Support copied from wepep250
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
28#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
29#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
30#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
31
32#define CONFIG_IMX_SERIAL1
33/*
34 * Select serial console configuration
35 */
36
37
38/*
Jon Loeliger079a1362007-07-10 10:12:10 -050039 * BOOTP options
40 */
41#define CONFIG_BOOTP_BOOTFILESIZE
42#define CONFIG_BOOTP_BOOTPATH
43#define CONFIG_BOOTP_GATEWAY
44#define CONFIG_BOOTP_HOSTNAME
45
46
47/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050048 * Command line configuration.
wdenk281e00a2004-08-01 22:48:16 +000049 */
Jon Loeliger46da1e92007-07-04 22:33:30 -050050#include <config_cmd_default.h>
wdenk281e00a2004-08-01 22:48:16 +000051
Jon Loeliger46da1e92007-07-04 22:33:30 -050052#define CONFIG_CMD_NET
53#define CONFIG_CMD_PING
54#define CONFIG_CMD_DHCP
55
56#undef CONFIG_CMD_LOADS
57#undef CONFIG_CMD_CONSOLE
58#undef CONFIG_CMD_AUTOSCRIPT
59
wdenk281e00a2004-08-01 22:48:16 +000060
61/*
62 * Boot options. Setting delay to -1 stops autostart count down.
63 * NOTE: Sending parameters to kernel depends on kernel version and
64 * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
65 * parameters at all! Do not get confused by them so.
66 */
67#define CONFIG_BOOTDELAY -1
68#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
69#define CONFIG_BOOTCOMMAND "bootm 10040000"
70#define CONFIG_SHOW_BOOT_PROGRESS
71#define CONFIG_ETHADDR 80:81:82:83:84:85
72#define CONFIG_NETMASK 255.255.255.0
73#define CONFIG_IPADDR 10.10.10.9
74#define CONFIG_SERVERIP 10.10.10.10
75
76/*
77 * General options for u-boot. Modify to save memory foot print
78 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_LONGHELP /* undef saves memory */
80#define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */
81#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
82#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
83#define CONFIG_SYS_MAXARGS 16 /* max command args */
84#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
wdenk281e00a2004-08-01 22:48:16 +000085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
87#define CONFIG_SYS_MEMTEST_END 0x08F00000
wdenk281e00a2004-08-01 22:48:16 +000088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */
wdenk281e00a2004-08-01 22:48:16 +000090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
92#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
wdenk281e00a2004-08-01 22:48:16 +000093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk281e00a2004-08-01 22:48:16 +000095#define CONFIG_BAUDRATE 115200
96/*
97 * Definitions related to passing arguments to kernel.
98 */
99#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
100#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
101#define CONFIG_INITRD_TAG 1 /* send initrd params */
102#undef CONFIG_VFD /* do not send framebuffer setup */
103
104
105/*
106 * Malloc pool need to host env + 128 Kb reserve for other allocations.
107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
wdenk281e00a2004-08-01 22:48:16 +0000109
110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk281e00a2004-08-01 22:48:16 +0000112
113#define CONFIG_STACKSIZE (120<<10) /* stack size */
114
115#ifdef CONFIG_USE_IRQ
116#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
117#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
118#endif
119
120/* SDRAM Setup Values
1210x910a8300 Precharge Command CAS 3
1220x910a8200 Precharge Command CAS 2
123
1240xa10a8300 AutoRefresh Command CAS 3
1250xa10a8200 Set AutoRefresh Command CAS 2 */
126
127#define PRECHARGE_CMD 0x910a8200
128#define AUTOREFRESH_CMD 0xa10a8200
wdenk281e00a2004-08-01 22:48:16 +0000129
130/*
131 * SDRAM Memory Map
132 */
133/* SH FIXME */
134#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
135#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
136#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
137
138/*
139 * Flash Controller settings
140 */
141
142/*
143 * Hardware drivers
144 */
145
146
147/*
148 * Configuration for FLASH memory for the Synertronixx board
149 */
150
151/* #define SCB9328_FLASH_32M */
152
153/* 32MB */
154#ifdef SCB9328_FLASH_32M
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
156#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
wdenk281e00a2004-08-01 22:48:16 +0000157#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
158#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
159#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
160#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
161#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
162#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
163#else
164
165/* 16MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
167#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
wdenk281e00a2004-08-01 22:48:16 +0000168#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
169#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
170#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
171#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
172#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
173#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
174#endif /* SCB9328_FLASH_32M */
175
176/* This should be defined if CFI FLASH device is present. Actually benefit
177 is not so clear to me. In other words we can provide more informations
178 to user, but this expects more complex flash handling we do not provide
179 now.*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#undef CONFIG_SYS_FLASH_CFI
wdenk281e00a2004-08-01 22:48:16 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */
183#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */
wdenk281e00a2004-08-01 22:48:16 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE
wdenk281e00a2004-08-01 22:48:16 +0000186
187/*
188 * This is setting for JFFS2 support in u-boot.
189 * Right now there is no gain for user, but later on booting kernel might be
190 * possible. Consider using XIP kernel running from flash to save RAM
191 * footprint.
Jon Loeliger079a1362007-07-10 10:12:10 -0500192 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
wdenk281e00a2004-08-01 22:48:16 +0000193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_JFFS2_FIRST_BANK 0
195#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
196#define CONFIG_SYS_JFFS2_NUM_BANKS 1
wdenk281e00a2004-08-01 22:48:16 +0000197
198/*
199 * Environment setup. Definitions of monitor location and size with
200 * definition of environment setup ends up in 2 possibilities.
201 * 1. Embeded environment - in u-boot code is space for environment
202 * 2. Environment is read from predefined sector of flash
203 * Right now we support 2. possiblity, but expecting no env placed
204 * on mentioned address right now. This also needs to provide whole
205 * sector for it - for us 256Kb is really waste of memory. U-boot uses
206 * default env. and until kernel parameters could be sent to kernel
207 * env. has no sense to us.
208 */
209
210/* Setup for PA23 which is Reset Default PA23 but has to become
211 CS5 */
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_GPR_A_VAL 0x00800000
214#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe
wdenk281e00a2004-08-01 22:48:16 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_MONITOR_BASE 0x10000000
217#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200218#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200219#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
220#define CONFIG_ENV_SIZE 0x20000
wdenk281e00a2004-08-01 22:48:16 +0000221
222#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
223
224/*
225 * CSxU_VAL:
226 * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
227 * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
228 *
229 * CSxL_VAL:
230 * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
231 * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
232 */
233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_CS0U_VAL 0x000F2000
235#define CONFIG_SYS_CS0L_VAL 0x11110d01
236#define CONFIG_SYS_CS1U_VAL 0x000F0a00
237#define CONFIG_SYS_CS1L_VAL 0x11110601
238#define CONFIG_SYS_CS2U_VAL 0x0
239#define CONFIG_SYS_CS2L_VAL 0x0
wdenk281e00a2004-08-01 22:48:16 +0000240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
242#define CONFIG_SYS_CS3L_VAL 0x00000303
wdenk281e00a2004-08-01 22:48:16 +0000243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_CS4U_VAL 0x000F0a00
245#define CONFIG_SYS_CS4L_VAL 0x11110301
wdenk281e00a2004-08-01 22:48:16 +0000246
247/* CNC == 3 too long
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248 #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
wdenk281e00a2004-08-01 22:48:16 +0000249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250/* #define CONFIG_SYS_CS5U_VAL 0x00008400
wdenk281e00a2004-08-01 22:48:16 +0000251 mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
252 kaum langsamer ist */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253/* #define CONFIG_SYS_CS5U_VAL 0x00009400
254 #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
wdenk281e00a2004-08-01 22:48:16 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_CS5U_VAL 0x00008400
257#define CONFIG_SYS_CS5L_VAL 0x00000D03
wdenk281e00a2004-08-01 22:48:16 +0000258
259#define CONFIG_DRIVER_DM9000 1
wdenk281e00a2004-08-01 22:48:16 +0000260#define CONFIG_DM9000_BASE 0x16000000
261#define DM9000_IO CONFIG_DM9000_BASE
262#define DM9000_DATA (CONFIG_DM9000_BASE+4)
wdenk281e00a2004-08-01 22:48:16 +0000263
264/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
265 f_ref=16,777MHz
266
267 0x002a141f: 191,9944MHz
268 0x040b2007: 144MHz
269 0x042a141f: 96MHz
270 0x0811140d: 64MHz
271 0x040e200e: 150MHz
272 0x00321431: 200MHz
273
274 0x08001800: 64MHz mit 16er Quarz
275 0x04001800: 96MHz mit 16er Quarz
276 0x04002400: 144MHz mit 16er Quarz
277
278 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
279 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
280
281#define CPU200
282
283#ifdef CPU200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_MPCTL0_VAL 0x00321431
wdenk281e00a2004-08-01 22:48:16 +0000285#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
wdenk281e00a2004-08-01 22:48:16 +0000287#endif
288
289/* #define BUS64 */
290#define BUS72
291
292#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_SPCTL0_VAL 0x04002400
wdenk281e00a2004-08-01 22:48:16 +0000294#endif
295
296#ifdef BUS96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_SPCTL0_VAL 0x04001800
wdenk281e00a2004-08-01 22:48:16 +0000298#endif
299
300#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_SPCTL0_VAL 0x08001800
wdenk281e00a2004-08-01 22:48:16 +0000302#endif
303
304/* Das ist der BCLK Divider, der aus der System PLL
305 BCLK und HCLK erzeugt:
306 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
307 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
308 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
309 0x2f001003 : 192MHz/5=38,4MHz
310 0x2f000003 : 64MHz/1
311 Bit 22: SPLL Restart
312 Bit 21: MPLL Restart */
313
314#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_CSCR_VAL 0x2f030003
wdenk281e00a2004-08-01 22:48:16 +0000316#endif
317
318#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_CSCR_VAL 0x2f030403
wdenk281e00a2004-08-01 22:48:16 +0000320#endif
321
322/*
323 * Well this has to be defined, but on the other hand it is used differently
324 * one may expect. For instance loadb command do not cares :-)
325 * So advice is - do not relay on this...
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_LOAD_ADDR 0x08400000
wdenk281e00a2004-08-01 22:48:16 +0000328
329#define MHZ16QUARZINUSE
330
331#ifdef MHZ16QUARZINUSE
332#define CONFIG_SYSPLL_CLK_FREQ 16000000
333#else
334#define CONFIG_SYSPLL_CLK_FREQ 16780000
335#endif
336
337#define CONFIG_SYS_CLK_FREQ 16780000
338
339/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_FMCR_VAL 0x00000001
wdenk281e00a2004-08-01 22:48:16 +0000341
342/* Bit[0:3] contain PERCLK1DIV for UART 1
343 0x000b00b ->b<- -> 192MHz/12=16MHz
344 0x000b00b ->8<- -> 144MHz/09=16MHz
345 0x000b00b ->3<- -> 64MHz/4=16MHz */
346
347#ifdef BUS96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_PCDR_VAL 0x000b00b5
wdenk281e00a2004-08-01 22:48:16 +0000349#endif
350
351#ifdef BUS64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_PCDR_VAL 0x000b00b3
wdenk281e00a2004-08-01 22:48:16 +0000353#endif
354
355#ifdef BUS72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_PCDR_VAL 0x000b00b8
wdenk281e00a2004-08-01 22:48:16 +0000357#endif
358
359#endif /* __CONFIG_H */