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Michael Trimarchi6b924872008-11-28 13:22:09 +01001/*
Ramneek Mehresh1b719e62011-03-23 15:20:43 +05302 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
Vivek Mahajan4ef01012009-05-25 17:23:16 +05303 *
Michael Trimarchi6b924872008-11-28 13:22:09 +01004 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
5 *
6 * Author: Tor Krill tor@excito.com
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Michael Trimarchi6b924872008-11-28 13:22:09 +01009 */
10
11#include <common.h>
12#include <pci.h>
13#include <usb.h>
Michael Trimarchi6b924872008-11-28 13:22:09 +010014#include <asm/io.h>
Vivek Mahajan4ef01012009-05-25 17:23:16 +053015#include <usb/ehci-fsl.h>
Ramneek Mehresh1b719e62011-03-23 15:20:43 +053016#include <hwconfig.h>
Michael Trimarchi6b924872008-11-28 13:22:09 +010017
Jean-Christophe PLAGNIOL-VILLARD2731b9a2009-04-03 12:46:58 +020018#include "ehci.h"
Michael Trimarchi6b924872008-11-28 13:22:09 +010019
Shengzhou Liu047cea32012-10-22 13:18:24 +080020/* Check USB PHY clock valid */
21static int usb_phy_clk_valid(struct usb_ehci *ehci)
22{
23 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
24 in_be32(&ehci->prictrl))) {
25 printf("USB PHY clock invalid!\n");
26 return 0;
27 } else {
28 return 1;
29 }
30}
31
Michael Trimarchi6b924872008-11-28 13:22:09 +010032/*
33 * Create the appropriate control structures to manage
34 * a new EHCI host controller.
35 *
36 * Excerpts from linux ehci fsl driver.
37 */
Troy Kisky127efc42013-10-10 15:27:57 -070038int ehci_hcd_init(int index, enum usb_init_type init,
39 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Michael Trimarchi6b924872008-11-28 13:22:09 +010040{
ramneek mehresh77354e92013-09-12 16:35:49 +053041 struct usb_ehci *ehci = NULL;
Ramneek Mehresh1b719e62011-03-23 15:20:43 +053042 const char *phy_type = NULL;
43 size_t len;
Nikhil Badola0ecb15c2013-12-19 11:08:46 +053044 char current_usb_controller[5];
Kumar Galadd22f7c2011-11-09 10:04:15 -060045#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
46 char usb_phy[5];
Ramneek Mehresh1b719e62011-03-23 15:20:43 +053047
48 usb_phy[0] = '\0';
Kumar Galadd22f7c2011-11-09 10:04:15 -060049#endif
Nikhil Badola0ecb15c2013-12-19 11:08:46 +053050 memset(current_usb_controller, '\0', 5);
51 snprintf(current_usb_controller, 4, "usb%d", index+1);
Michael Trimarchi6b924872008-11-28 13:22:09 +010052
ramneek mehresh77354e92013-09-12 16:35:49 +053053 switch (index) {
54 case 0:
55 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
56 break;
57 case 1:
58 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
59 break;
60 default:
61 printf("ERROR: wrong controller index!!\n");
62 break;
63 };
64
Lucas Stach676ae062012-09-26 00:14:35 +020065 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
66 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
67 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Michael Trimarchi6b924872008-11-28 13:22:09 +010068
Michael Trimarchi6b924872008-11-28 13:22:09 +010069 /* Set to Host mode */
Vivek Mahajan08066152009-06-19 17:56:00 +053070 setbits_le32(&ehci->usbmode, CM_HOST);
Michael Trimarchi6b924872008-11-28 13:22:09 +010071
Vivek Mahajan08066152009-06-19 17:56:00 +053072 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
73 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
Michael Trimarchi6b924872008-11-28 13:22:09 +010074
75 /* Init phy */
Nikhil Badola0ecb15c2013-12-19 11:08:46 +053076 if (hwconfig_sub(current_usb_controller, "phy_type"))
77 phy_type = hwconfig_subarg(current_usb_controller,
78 "phy_type", &len);
Vivek Mahajan4ef01012009-05-25 17:23:16 +053079 else
Ramneek Mehresh1b719e62011-03-23 15:20:43 +053080 phy_type = getenv("usb_phy_type");
81
82 if (!phy_type) {
83#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
84 /* if none specified assume internal UTMI */
85 strcpy(usb_phy, "utmi");
86 phy_type = usb_phy;
87#else
88 printf("WARNING: USB phy type not defined !!\n");
89 return -1;
90#endif
91 }
92
Nikhil Badola91d77462014-02-17 16:58:36 +053093 if (!strncmp(phy_type, "utmi", 4)) {
Ramneek Mehresh1b719e62011-03-23 15:20:43 +053094#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
95 setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
96 setbits_be32(&ehci->control, UTMI_PHY_EN);
97 udelay(1000); /* delay required for PHY Clk to appear */
98#endif
Lucas Stach676ae062012-09-26 00:14:35 +020099 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
Shengzhou Liu047cea32012-10-22 13:18:24 +0800100 setbits_be32(&ehci->control, USB_EN);
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530101 } else {
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530102 setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
Shengzhou Liu047cea32012-10-22 13:18:24 +0800103 clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530104 udelay(1000); /* delay required for PHY Clk to appear */
Shengzhou Liu047cea32012-10-22 13:18:24 +0800105 if (!usb_phy_clk_valid(ehci))
106 return -EINVAL;
Lucas Stach676ae062012-09-26 00:14:35 +0200107 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530108 }
Michael Trimarchi6b924872008-11-28 13:22:09 +0100109
Vivek Mahajan08066152009-06-19 17:56:00 +0530110 out_be32(&ehci->prictrl, 0x0000000c);
111 out_be32(&ehci->age_cnt_limit, 0x00000040);
112 out_be32(&ehci->sictrl, 0x00000001);
Michael Trimarchi6b924872008-11-28 13:22:09 +0100113
Vivek Mahajan08066152009-06-19 17:56:00 +0530114 in_le32(&ehci->usbmode);
Michael Trimarchi6b924872008-11-28 13:22:09 +0100115
116 return 0;
117}
118
119/*
120 * Destroy the appropriate control structures corresponding
121 * the the EHCI host controller.
122 */
Lucas Stach676ae062012-09-26 00:14:35 +0200123int ehci_hcd_stop(int index)
Michael Trimarchi6b924872008-11-28 13:22:09 +0100124{
125 return 0;
126}