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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Freescale Three Speed Ethernet Controller driver
wdenk42d1f032003-10-15 23:53:47 +00003 *
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
6 * herein by reference.
7 *
Claudiu Manoilaec84bf2013-09-30 12:44:42 +03008 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00009 * (C) Copyright 2003, Motorola, Inc.
wdenk42d1f032003-10-15 23:53:47 +000010 * author Andy Fleming
11 *
12 */
13
14#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000015#include <common.h>
16#include <malloc.h>
17#include <net.h>
18#include <command.h>
Andy Flemingdd3d1f52008-08-31 16:33:25 -050019#include <tsec.h>
Andy Fleming063c1262011-04-08 02:10:54 -050020#include <fsl_mdio.h>
Kim Phillips0d071cd2009-08-24 14:32:26 -050021#include <asm/errno.h>
chenhui zhaoaada81d2011-10-03 08:38:50 -050022#include <asm/processor.h>
Alison Wang52d00a82014-09-05 13:52:38 +080023#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000024
Wolfgang Denkd87080b2006-03-31 18:32:53 +020025DECLARE_GLOBAL_DATA_PTR;
26
Marian Balakowicz63ff0042005-10-28 22:30:33 +020027#define TX_BUF_CNT 2
wdenk42d1f032003-10-15 23:53:47 +000028
Claudiu Manoil18b338f2013-09-30 12:44:44 +030029static uint rx_idx; /* index of the current RX buffer */
30static uint tx_idx; /* index of the current TX buffer */
wdenk42d1f032003-10-15 23:53:47 +000031
wdenk42d1f032003-10-15 23:53:47 +000032#ifdef __GNUC__
Claudiu Manoil9c9141f2013-10-04 19:13:53 +030033static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
34static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
35
wdenk42d1f032003-10-15 23:53:47 +000036#else
37#error "rtx must be 64-bit aligned"
38#endif
39
Joe Hershbergerc8a60b52012-05-21 09:46:36 +000040static int tsec_send(struct eth_device *dev, void *packet, int length);
chenhui zhaoaada81d2011-10-03 08:38:50 -050041
Andy Fleming75b9d4a2008-08-31 16:33:26 -050042/* Default initializations for TSEC controllers. */
43
44static struct tsec_info_struct tsec_info[] = {
45#ifdef CONFIG_TSEC1
46 STD_TSEC_INFO(1), /* TSEC1 */
47#endif
48#ifdef CONFIG_TSEC2
49 STD_TSEC_INFO(2), /* TSEC2 */
50#endif
51#ifdef CONFIG_MPC85XX_FEC
52 {
Claudiu Manoilaec84bf2013-09-30 12:44:42 +030053 .regs = TSEC_GET_REGS(2, 0x2000),
Andy Fleming75b9d4a2008-08-31 16:33:26 -050054 .devname = CONFIG_MPC85XX_FEC_NAME,
55 .phyaddr = FEC_PHY_ADDR,
Andy Fleming063c1262011-04-08 02:10:54 -050056 .flags = FEC_FLAGS,
57 .mii_devname = DEFAULT_MII_NAME
Andy Fleming75b9d4a2008-08-31 16:33:26 -050058 }, /* FEC */
59#endif
60#ifdef CONFIG_TSEC3
61 STD_TSEC_INFO(3), /* TSEC3 */
62#endif
63#ifdef CONFIG_TSEC4
64 STD_TSEC_INFO(4), /* TSEC4 */
65#endif
66};
67
Andy Fleming2abe3612008-08-31 16:33:27 -050068#define TBIANA_SETTINGS ( \
69 TBIANA_ASYMMETRIC_PAUSE \
70 | TBIANA_SYMMETRIC_PAUSE \
71 | TBIANA_FULL_DUPLEX \
72 )
73
Felix Radensky90b5bf22010-06-28 01:57:39 +030074/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
75#ifndef CONFIG_TSEC_TBICR_SETTINGS
Kumar Gala72c96a62010-12-01 22:55:54 -060076#define CONFIG_TSEC_TBICR_SETTINGS ( \
Andy Fleming2abe3612008-08-31 16:33:27 -050077 TBICR_PHY_RESET \
Kumar Gala72c96a62010-12-01 22:55:54 -060078 | TBICR_ANEG_ENABLE \
Andy Fleming2abe3612008-08-31 16:33:27 -050079 | TBICR_FULL_DUPLEX \
80 | TBICR_SPEED1_SET \
81 )
Felix Radensky90b5bf22010-06-28 01:57:39 +030082#endif /* CONFIG_TSEC_TBICR_SETTINGS */
Peter Tyser46e91672009-11-03 17:52:07 -060083
Andy Fleming2abe3612008-08-31 16:33:27 -050084/* Configure the TBI for SGMII operation */
85static void tsec_configure_serdes(struct tsec_private *priv)
86{
Peter Tyserc6dbdfd2009-11-09 13:09:46 -060087 /* Access TBI PHY registers at given TSEC register offset as opposed
88 * to the register offset used for external PHY accesses */
Andy Fleming063c1262011-04-08 02:10:54 -050089 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
90 0, TBI_ANA, TBIANA_SETTINGS);
91 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
92 0, TBI_TBICON, TBICON_CLK_SELECT);
93 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
94 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
Andy Fleming2abe3612008-08-31 16:33:27 -050095}
michael.firth@bt.com55fe7c52008-01-16 11:40:51 +000096
David Updegraff53a5c422007-06-11 10:41:07 -050097#ifdef CONFIG_MCAST_TFTP
98
99/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
100
101/* Set the appropriate hash bit for the given addr */
102
103/* The algorithm works like so:
104 * 1) Take the Destination Address (ie the multicast address), and
105 * do a CRC on it (little endian), and reverse the bits of the
106 * result.
107 * 2) Use the 8 most significant bits as a hash into a 256-entry
108 * table. The table is controlled through 8 32-bit registers:
Claudiu Manoil876d4512013-09-30 12:44:40 +0300109 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
110 * 255. This means that the 3 most significant bits in the
David Updegraff53a5c422007-06-11 10:41:07 -0500111 * hash index which gaddr register to use, and the 5 other bits
112 * indicate which bit (assuming an IBM numbering scheme, which
Claudiu Manoil876d4512013-09-30 12:44:40 +0300113 * for PowerPC (tm) is usually the case) in the register holds
David Updegraff53a5c422007-06-11 10:41:07 -0500114 * the entry. */
115static int
Claudiu Manoil9c4cffa2013-09-30 12:44:39 +0300116tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
David Updegraff53a5c422007-06-11 10:41:07 -0500117{
Claudiu Manoilb2002042013-09-30 12:44:41 +0300118 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoil876d4512013-09-30 12:44:40 +0300119 struct tsec __iomem *regs = priv->regs;
120 u32 result, value;
121 u8 whichbit, whichreg;
David Updegraff53a5c422007-06-11 10:41:07 -0500122
Claudiu Manoil876d4512013-09-30 12:44:40 +0300123 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
124 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
125 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
David Updegraff53a5c422007-06-11 10:41:07 -0500126
Claudiu Manoil876d4512013-09-30 12:44:40 +0300127 value = 1 << (31-whichbit);
David Updegraff53a5c422007-06-11 10:41:07 -0500128
Claudiu Manoil876d4512013-09-30 12:44:40 +0300129 if (set)
130 setbits_be32(&regs->hash.gaddr0 + whichreg, value);
131 else
132 clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
133
David Updegraff53a5c422007-06-11 10:41:07 -0500134 return 0;
135}
136#endif /* Multicast TFTP ? */
Mingkai Hu90751912011-01-27 12:52:46 +0800137
138/* Initialized required registers to appropriate values, zeroing
139 * those we don't care about (unless zero is bad, in which case,
140 * choose a more appropriate value)
141 */
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300142static void init_registers(struct tsec __iomem *regs)
Mingkai Hu90751912011-01-27 12:52:46 +0800143{
144 /* Clear IEVENT */
145 out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
146
147 out_be32(&regs->imask, IMASK_INIT_CLEAR);
148
149 out_be32(&regs->hash.iaddr0, 0);
150 out_be32(&regs->hash.iaddr1, 0);
151 out_be32(&regs->hash.iaddr2, 0);
152 out_be32(&regs->hash.iaddr3, 0);
153 out_be32(&regs->hash.iaddr4, 0);
154 out_be32(&regs->hash.iaddr5, 0);
155 out_be32(&regs->hash.iaddr6, 0);
156 out_be32(&regs->hash.iaddr7, 0);
157
158 out_be32(&regs->hash.gaddr0, 0);
159 out_be32(&regs->hash.gaddr1, 0);
160 out_be32(&regs->hash.gaddr2, 0);
161 out_be32(&regs->hash.gaddr3, 0);
162 out_be32(&regs->hash.gaddr4, 0);
163 out_be32(&regs->hash.gaddr5, 0);
164 out_be32(&regs->hash.gaddr6, 0);
165 out_be32(&regs->hash.gaddr7, 0);
166
167 out_be32(&regs->rctrl, 0x00000000);
168
169 /* Init RMON mib registers */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300170 memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
Mingkai Hu90751912011-01-27 12:52:46 +0800171
172 out_be32(&regs->rmon.cam1, 0xffffffff);
173 out_be32(&regs->rmon.cam2, 0xffffffff);
174
175 out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
176
177 out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
178
179 out_be32(&regs->attr, ATTR_INIT_SETTINGS);
180 out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
181
182}
183
184/* Configure maccfg2 based on negotiated speed and duplex
185 * reported by PHY handling code
186 */
Andy Fleming063c1262011-04-08 02:10:54 -0500187static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
Mingkai Hu90751912011-01-27 12:52:46 +0800188{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300189 struct tsec __iomem *regs = priv->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800190 u32 ecntrl, maccfg2;
191
Andy Fleming063c1262011-04-08 02:10:54 -0500192 if (!phydev->link) {
193 printf("%s: No link.\n", phydev->dev->name);
Mingkai Hu90751912011-01-27 12:52:46 +0800194 return;
195 }
196
197 /* clear all bits relative with interface mode */
198 ecntrl = in_be32(&regs->ecntrl);
199 ecntrl &= ~ECNTRL_R100;
200
201 maccfg2 = in_be32(&regs->maccfg2);
202 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
203
Andy Fleming063c1262011-04-08 02:10:54 -0500204 if (phydev->duplex)
Mingkai Hu90751912011-01-27 12:52:46 +0800205 maccfg2 |= MACCFG2_FULL_DUPLEX;
206
Andy Fleming063c1262011-04-08 02:10:54 -0500207 switch (phydev->speed) {
Mingkai Hu90751912011-01-27 12:52:46 +0800208 case 1000:
209 maccfg2 |= MACCFG2_GMII;
210 break;
211 case 100:
212 case 10:
213 maccfg2 |= MACCFG2_MII;
214
215 /* Set R100 bit in all modes although
216 * it is only used in RGMII mode
217 */
Andy Fleming063c1262011-04-08 02:10:54 -0500218 if (phydev->speed == 100)
Mingkai Hu90751912011-01-27 12:52:46 +0800219 ecntrl |= ECNTRL_R100;
220 break;
221 default:
Andy Fleming063c1262011-04-08 02:10:54 -0500222 printf("%s: Speed was bad\n", phydev->dev->name);
Mingkai Hu90751912011-01-27 12:52:46 +0800223 break;
224 }
225
226 out_be32(&regs->ecntrl, ecntrl);
227 out_be32(&regs->maccfg2, maccfg2);
228
Andy Fleming063c1262011-04-08 02:10:54 -0500229 printf("Speed: %d, %s duplex%s\n", phydev->speed,
230 (phydev->duplex) ? "full" : "half",
231 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
Mingkai Hu90751912011-01-27 12:52:46 +0800232}
233
chenhui zhaoaada81d2011-10-03 08:38:50 -0500234#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
235/*
236 * When MACCFG1[Rx_EN] is enabled during system boot as part
237 * of the eTSEC port initialization sequence,
238 * the eTSEC Rx logic may not be properly initialized.
239 */
240void redundant_init(struct eth_device *dev)
241{
242 struct tsec_private *priv = dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300243 struct tsec __iomem *regs = priv->regs;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500244 uint t, count = 0;
245 int fail = 1;
246 static const u8 pkt[] = {
247 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
248 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
249 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
250 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
251 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
252 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
253 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
254 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
255 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
256 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
257 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
258 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
259 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
260 0x71, 0x72};
261
262 /* Enable promiscuous mode */
263 setbits_be32(&regs->rctrl, 0x8);
264 /* Enable loopback mode */
265 setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
266 /* Enable transmit and receive */
267 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
268
269 /* Tell the DMA it is clear to go */
270 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
271 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
272 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
273 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
274
275 do {
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300276 uint16_t status;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500277 tsec_send(dev, (void *)pkt, sizeof(pkt));
278
279 /* Wait for buffer to be received */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300280 for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
chenhui zhaoaada81d2011-10-03 08:38:50 -0500281 if (t >= 10 * TOUT_LOOP) {
282 printf("%s: tsec: rx error\n", dev->name);
283 break;
284 }
285 }
286
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500287 if (!memcmp(pkt, (void *)net_rx_packets[rx_idx], sizeof(pkt)))
chenhui zhaoaada81d2011-10-03 08:38:50 -0500288 fail = 0;
289
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300290 out_be16(&rxbd[rx_idx].length, 0);
291 status = RXBD_EMPTY;
292 if ((rx_idx + 1) == PKTBUFSRX)
293 status |= RXBD_WRAP;
294 out_be16(&rxbd[rx_idx].status, status);
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300295 rx_idx = (rx_idx + 1) % PKTBUFSRX;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500296
297 if (in_be32(&regs->ievent) & IEVENT_BSY) {
298 out_be32(&regs->ievent, IEVENT_BSY);
299 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
300 }
301 if (fail) {
302 printf("loopback recv packet error!\n");
303 clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
304 udelay(1000);
305 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
306 }
307 } while ((count++ < 4) && (fail == 1));
308
309 if (fail)
310 panic("eTSEC init fail!\n");
311 /* Disable promiscuous mode */
312 clrbits_be32(&regs->rctrl, 0x8);
313 /* Disable loopback mode */
314 clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
315}
316#endif
317
Mingkai Hu90751912011-01-27 12:52:46 +0800318/* Set up the buffers and their descriptors, and bring up the
319 * interface
320 */
321static void startup_tsec(struct eth_device *dev)
322{
Mingkai Hu90751912011-01-27 12:52:46 +0800323 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300324 struct tsec __iomem *regs = priv->regs;
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300325 uint16_t status;
326 int i;
Mingkai Hu90751912011-01-27 12:52:46 +0800327
Andy Fleming063c1262011-04-08 02:10:54 -0500328 /* reset the indices to zero */
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300329 rx_idx = 0;
330 tx_idx = 0;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500331#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
332 uint svr;
333#endif
Andy Fleming063c1262011-04-08 02:10:54 -0500334
Mingkai Hu90751912011-01-27 12:52:46 +0800335 /* Point to the buffer descriptors */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300336 out_be32(&regs->tbase, (u32)&txbd[0]);
337 out_be32(&regs->rbase, (u32)&rxbd[0]);
Mingkai Hu90751912011-01-27 12:52:46 +0800338
339 /* Initialize the Rx Buffer descriptors */
340 for (i = 0; i < PKTBUFSRX; i++) {
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300341 out_be16(&rxbd[i].status, RXBD_EMPTY);
342 out_be16(&rxbd[i].length, 0);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500343 out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]);
Mingkai Hu90751912011-01-27 12:52:46 +0800344 }
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300345 status = in_be16(&rxbd[PKTBUFSRX - 1].status);
346 out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
Mingkai Hu90751912011-01-27 12:52:46 +0800347
348 /* Initialize the TX Buffer Descriptors */
349 for (i = 0; i < TX_BUF_CNT; i++) {
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300350 out_be16(&txbd[i].status, 0);
351 out_be16(&txbd[i].length, 0);
352 out_be32(&txbd[i].bufptr, 0);
Mingkai Hu90751912011-01-27 12:52:46 +0800353 }
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300354 status = in_be16(&txbd[TX_BUF_CNT - 1].status);
355 out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
Mingkai Hu90751912011-01-27 12:52:46 +0800356
chenhui zhaoaada81d2011-10-03 08:38:50 -0500357#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
358 svr = get_svr();
359 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
360 redundant_init(dev);
361#endif
Mingkai Hu90751912011-01-27 12:52:46 +0800362 /* Enable Transmit and Receive */
363 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
364
365 /* Tell the DMA it is clear to go */
366 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
367 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
368 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
369 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
370}
371
372/* This returns the status bits of the device. The return value
373 * is never checked, and this is what the 8260 driver did, so we
374 * do the same. Presumably, this would be zero if there were no
375 * errors
376 */
Joe Hershbergerc8a60b52012-05-21 09:46:36 +0000377static int tsec_send(struct eth_device *dev, void *packet, int length)
Mingkai Hu90751912011-01-27 12:52:46 +0800378{
Mingkai Hu90751912011-01-27 12:52:46 +0800379 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300380 struct tsec __iomem *regs = priv->regs;
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300381 uint16_t status;
382 int result = 0;
383 int i;
Mingkai Hu90751912011-01-27 12:52:46 +0800384
385 /* Find an empty buffer descriptor */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300386 for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
Mingkai Hu90751912011-01-27 12:52:46 +0800387 if (i >= TOUT_LOOP) {
388 debug("%s: tsec: tx buffers full\n", dev->name);
389 return result;
390 }
391 }
392
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300393 out_be32(&txbd[tx_idx].bufptr, (u32)packet);
394 out_be16(&txbd[tx_idx].length, length);
395 status = in_be16(&txbd[tx_idx].status);
396 out_be16(&txbd[tx_idx].status, status |
397 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
Mingkai Hu90751912011-01-27 12:52:46 +0800398
399 /* Tell the DMA to go */
400 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
401
402 /* Wait for buffer to be transmitted */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300403 for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
Mingkai Hu90751912011-01-27 12:52:46 +0800404 if (i >= TOUT_LOOP) {
405 debug("%s: tsec: tx error\n", dev->name);
406 return result;
407 }
408 }
409
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300410 tx_idx = (tx_idx + 1) % TX_BUF_CNT;
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300411 result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
Mingkai Hu90751912011-01-27 12:52:46 +0800412
413 return result;
414}
415
416static int tsec_recv(struct eth_device *dev)
417{
Mingkai Hu90751912011-01-27 12:52:46 +0800418 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300419 struct tsec __iomem *regs = priv->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800420
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300421 while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
422 int length = in_be16(&rxbd[rx_idx].length);
423 uint16_t status = in_be16(&rxbd[rx_idx].status);
Mingkai Hu90751912011-01-27 12:52:46 +0800424
425 /* Send the packet up if there were no errors */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300426 if (!(status & RXBD_STATS))
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500427 net_process_received_packet(net_rx_packets[rx_idx],
428 length - 4);
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300429 else
430 printf("Got error %x\n", (status & RXBD_STATS));
Mingkai Hu90751912011-01-27 12:52:46 +0800431
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300432 out_be16(&rxbd[rx_idx].length, 0);
Mingkai Hu90751912011-01-27 12:52:46 +0800433
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300434 status = RXBD_EMPTY;
Mingkai Hu90751912011-01-27 12:52:46 +0800435 /* Set the wrap bit if this is the last element in the list */
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300436 if ((rx_idx + 1) == PKTBUFSRX)
437 status |= RXBD_WRAP;
438 out_be16(&rxbd[rx_idx].status, status);
Mingkai Hu90751912011-01-27 12:52:46 +0800439
Claudiu Manoil18b338f2013-09-30 12:44:44 +0300440 rx_idx = (rx_idx + 1) % PKTBUFSRX;
Mingkai Hu90751912011-01-27 12:52:46 +0800441 }
442
443 if (in_be32(&regs->ievent) & IEVENT_BSY) {
444 out_be32(&regs->ievent, IEVENT_BSY);
445 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
446 }
447
448 return -1;
449
450}
451
452/* Stop the interface */
453static void tsec_halt(struct eth_device *dev)
454{
455 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300456 struct tsec __iomem *regs = priv->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800457
458 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
459 setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
460
461 while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
462 != (IEVENT_GRSC | IEVENT_GTSC))
463 ;
464
465 clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
466
467 /* Shut down the PHY, as needed */
Andy Fleming063c1262011-04-08 02:10:54 -0500468 phy_shutdown(priv->phydev);
Mingkai Hu90751912011-01-27 12:52:46 +0800469}
470
471/* Initializes data structures and registers for the controller,
472 * and brings the interface up. Returns the link status, meaning
473 * that it returns success if the link is up, failure otherwise.
474 * This allows u-boot to find the first active controller.
475 */
476static int tsec_init(struct eth_device *dev, bd_t * bd)
477{
Mingkai Hu90751912011-01-27 12:52:46 +0800478 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300479 struct tsec __iomem *regs = priv->regs;
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300480 u32 tempval;
Timur Tabi11af8d62012-07-09 08:52:43 +0000481 int ret;
Mingkai Hu90751912011-01-27 12:52:46 +0800482
483 /* Make sure the controller is stopped */
484 tsec_halt(dev);
485
486 /* Init MACCFG2. Defaults to GMII */
487 out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
488
489 /* Init ECNTRL */
490 out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
491
492 /* Copy the station address into the address registers.
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300493 * For a station address of 0x12345678ABCD in transmission
494 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
495 * MACnADDR2 is set to 0x34120000.
496 */
497 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
498 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
Mingkai Hu90751912011-01-27 12:52:46 +0800499
500 out_be32(&regs->macstnaddr1, tempval);
501
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300502 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
Mingkai Hu90751912011-01-27 12:52:46 +0800503
504 out_be32(&regs->macstnaddr2, tempval);
505
Mingkai Hu90751912011-01-27 12:52:46 +0800506 /* Clear out (for the most part) the other registers */
507 init_registers(regs);
508
509 /* Ready the device for tx/rx */
510 startup_tsec(dev);
511
Andy Fleming063c1262011-04-08 02:10:54 -0500512 /* Start up the PHY */
Timur Tabi11af8d62012-07-09 08:52:43 +0000513 ret = phy_startup(priv->phydev);
514 if (ret) {
515 printf("Could not initialize PHY %s\n",
516 priv->phydev->dev->name);
517 return ret;
518 }
Andy Fleming063c1262011-04-08 02:10:54 -0500519
520 adjust_link(priv, priv->phydev);
521
Mingkai Hu90751912011-01-27 12:52:46 +0800522 /* If there's no link, fail */
Andy Fleming063c1262011-04-08 02:10:54 -0500523 return priv->phydev->link ? 0 : -1;
Mingkai Hu90751912011-01-27 12:52:46 +0800524}
525
Andy Fleming063c1262011-04-08 02:10:54 -0500526static phy_interface_t tsec_get_interface(struct tsec_private *priv)
527{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300528 struct tsec __iomem *regs = priv->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500529 u32 ecntrl;
530
531 ecntrl = in_be32(&regs->ecntrl);
532
533 if (ecntrl & ECNTRL_SGMII_MODE)
534 return PHY_INTERFACE_MODE_SGMII;
535
536 if (ecntrl & ECNTRL_TBI_MODE) {
537 if (ecntrl & ECNTRL_REDUCED_MODE)
538 return PHY_INTERFACE_MODE_RTBI;
539 else
540 return PHY_INTERFACE_MODE_TBI;
541 }
542
543 if (ecntrl & ECNTRL_REDUCED_MODE) {
544 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
545 return PHY_INTERFACE_MODE_RMII;
546 else {
547 phy_interface_t interface = priv->interface;
548
549 /*
550 * This isn't autodetected, so it must
551 * be set by the platform code.
552 */
553 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
554 (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
555 (interface == PHY_INTERFACE_MODE_RGMII_RXID))
556 return interface;
557
558 return PHY_INTERFACE_MODE_RGMII;
559 }
560 }
561
562 if (priv->flags & TSEC_GIGABIT)
563 return PHY_INTERFACE_MODE_GMII;
564
565 return PHY_INTERFACE_MODE_MII;
566}
567
568
Mingkai Hu90751912011-01-27 12:52:46 +0800569/* Discover which PHY is attached to the device, and configure it
570 * properly. If the PHY is not recognized, then return 0
571 * (failure). Otherwise, return 1
572 */
573static int init_phy(struct eth_device *dev)
574{
575 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Andy Fleming063c1262011-04-08 02:10:54 -0500576 struct phy_device *phydev;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300577 struct tsec __iomem *regs = priv->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500578 u32 supported = (SUPPORTED_10baseT_Half |
579 SUPPORTED_10baseT_Full |
580 SUPPORTED_100baseT_Half |
581 SUPPORTED_100baseT_Full);
582
583 if (priv->flags & TSEC_GIGABIT)
584 supported |= SUPPORTED_1000baseT_Full;
Mingkai Hu90751912011-01-27 12:52:46 +0800585
586 /* Assign a Physical address to the TBI */
587 out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
588
Andy Fleming063c1262011-04-08 02:10:54 -0500589 priv->interface = tsec_get_interface(priv);
Mingkai Hu90751912011-01-27 12:52:46 +0800590
Andy Fleming063c1262011-04-08 02:10:54 -0500591 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
Mingkai Hu90751912011-01-27 12:52:46 +0800592 tsec_configure_serdes(priv);
593
Andy Fleming063c1262011-04-08 02:10:54 -0500594 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
Claudiu Manoil7f233c02013-12-10 15:21:04 +0200595 if (!phydev)
596 return 0;
Mingkai Hu90751912011-01-27 12:52:46 +0800597
Andy Fleming063c1262011-04-08 02:10:54 -0500598 phydev->supported &= supported;
599 phydev->advertising = phydev->supported;
600
601 priv->phydev = phydev;
602
603 phy_config(phydev);
Mingkai Hu90751912011-01-27 12:52:46 +0800604
605 return 1;
606}
607
608/* Initialize device structure. Returns success if PHY
609 * initialization succeeded (i.e. if it recognizes the PHY)
610 */
611static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
612{
613 struct eth_device *dev;
614 int i;
615 struct tsec_private *priv;
616
617 dev = (struct eth_device *)malloc(sizeof *dev);
618
619 if (NULL == dev)
620 return 0;
621
622 memset(dev, 0, sizeof *dev);
623
624 priv = (struct tsec_private *)malloc(sizeof(*priv));
625
626 if (NULL == priv)
627 return 0;
628
Mingkai Hu90751912011-01-27 12:52:46 +0800629 priv->regs = tsec_info->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800630 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
631
632 priv->phyaddr = tsec_info->phyaddr;
633 priv->flags = tsec_info->flags;
634
635 sprintf(dev->name, tsec_info->devname);
Andy Fleming063c1262011-04-08 02:10:54 -0500636 priv->interface = tsec_info->interface;
637 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
Mingkai Hu90751912011-01-27 12:52:46 +0800638 dev->iobase = 0;
639 dev->priv = priv;
640 dev->init = tsec_init;
641 dev->halt = tsec_halt;
642 dev->send = tsec_send;
643 dev->recv = tsec_recv;
644#ifdef CONFIG_MCAST_TFTP
645 dev->mcast = tsec_mcast_addr;
646#endif
647
648 /* Tell u-boot to get the addr from the env */
649 for (i = 0; i < 6; i++)
650 dev->enetaddr[i] = 0;
651
652 eth_register(dev);
653
654 /* Reset the MAC */
655 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
656 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
657 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
658
Mingkai Hu90751912011-01-27 12:52:46 +0800659 /* Try to initialize PHY here, and return */
660 return init_phy(dev);
661}
662
663/*
664 * Initialize all the TSEC devices
665 *
666 * Returns the number of TSEC devices that were initialized
667 */
668int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
669{
670 int i;
671 int ret, count = 0;
672
673 for (i = 0; i < num; i++) {
674 ret = tsec_initialize(bis, &tsecs[i]);
675 if (ret > 0)
676 count += ret;
677 }
678
679 return count;
680}
681
682int tsec_standard_init(bd_t *bis)
683{
Andy Fleming063c1262011-04-08 02:10:54 -0500684 struct fsl_pq_mdio_info info;
685
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300686 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
Andy Fleming063c1262011-04-08 02:10:54 -0500687 info.name = DEFAULT_MII_NAME;
688
689 fsl_pq_mdio_init(bis, &info);
690
Mingkai Hu90751912011-01-27 12:52:46 +0800691 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
692}