blob: 5bf2364ee2d7e00a70824eb204ced9585d9a3612 [file] [log] [blame]
Joe Hamman8ac27322007-08-09 15:10:53 -05001/*
2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman joe.hamman@embeddedspecialties.com
5 *
6 * Copyright 2004 Freescale Semiconductor.
7 * Jeff Brown
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <common.h>
32#include <command.h>
33#include <pci.h>
34#include <asm/processor.h>
35#include <asm/immap_86xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050036#include <asm/fsl_pci.h>
Kumar Gala9bd4e592008-08-26 15:01:37 -050037#include <asm/fsl_ddr_sdram.h>
Jon Loeliger13f54332008-02-18 14:01:56 -060038#include <libfdt.h>
39#include <fdt_support.h>
Joe Hamman8ac27322007-08-09 15:10:53 -050040
Joe Hamman8ac27322007-08-09 15:10:53 -050041long int fixed_sdram (void);
42
43int board_early_init_f (void)
44{
45 return 0;
46}
47
48int checkboard (void)
49{
50 puts ("Board: Wind River SBC8641D\n");
51
Joe Hamman8ac27322007-08-09 15:10:53 -050052 return 0;
53}
54
Becky Bruce9973e3c2008-06-09 16:03:40 -050055phys_size_t initdram (int board_type)
Joe Hamman8ac27322007-08-09 15:10:53 -050056{
57 long dram_size = 0;
58
59#if defined(CONFIG_SPD_EEPROM)
Kumar Gala9bd4e592008-08-26 15:01:37 -050060 dram_size = fsl_ddr_sdram();
Joe Hamman8ac27322007-08-09 15:10:53 -050061#else
62 dram_size = fixed_sdram ();
63#endif
64
Joe Hamman8ac27322007-08-09 15:10:53 -050065 puts (" DDR: ");
66 return dram_size;
67}
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#if defined(CONFIG_SYS_DRAM_TEST)
Joe Hamman8ac27322007-08-09 15:10:53 -050070int testdram (void)
71{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
73 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Joe Hamman8ac27322007-08-09 15:10:53 -050074 uint *p;
75
76 puts ("SDRAM test phase 1:\n");
77 for (p = pstart; p < pend; p++)
78 *p = 0xaaaaaaaa;
79
80 for (p = pstart; p < pend; p++) {
81 if (*p != 0xaaaaaaaa) {
82 printf ("SDRAM test fails at: %08x\n", (uint) p);
83 return 1;
84 }
85 }
86
87 puts ("SDRAM test phase 2:\n");
88 for (p = pstart; p < pend; p++)
89 *p = 0x55555555;
90
91 for (p = pstart; p < pend; p++) {
92 if (*p != 0x55555555) {
93 printf ("SDRAM test fails at: %08x\n", (uint) p);
94 return 1;
95 }
96 }
97
98 puts ("SDRAM test passed.\n");
99 return 0;
100}
101#endif
102
103#if !defined(CONFIG_SPD_EEPROM)
104/*
105 * Fixed sdram init -- doesn't use serial presence detect.
106 */
107long int fixed_sdram (void)
108{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#if !defined(CONFIG_SYS_RAMBOOT)
110 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Joe Hamman8ac27322007-08-09 15:10:53 -0500111 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
114 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
115 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
116 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
117 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
118 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
119 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
120 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
121 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
122 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
123 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
124 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500125 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500127 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
129 ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
130 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
131 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
132 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
Joe Hamman8ac27322007-08-09 15:10:53 -0500133
134 asm ("sync;isync");
135
136 udelay (500);
137
Peter Tysere7ee23e2009-07-17 10:14:45 -0500138 ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
Joe Hamman8ac27322007-08-09 15:10:53 -0500139 asm ("sync; isync");
140
141 udelay (500);
142 ddr = &immap->im_ddr2;
143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
145 ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
146 ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
147 ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
148 ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
149 ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
150 ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
151 ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
152 ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
153 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
154 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
155 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500156 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500158 ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
160 ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
161 ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
162 ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
163 ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
Joe Hamman8ac27322007-08-09 15:10:53 -0500164
165 asm ("sync;isync");
166
167 udelay (500);
168
Peter Tysere7ee23e2009-07-17 10:14:45 -0500169 ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
Joe Hamman8ac27322007-08-09 15:10:53 -0500170 asm ("sync; isync");
171
172 udelay (500);
173#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Joe Hamman8ac27322007-08-09 15:10:53 -0500175}
176#endif /* !defined(CONFIG_SPD_EEPROM) */
177
178#if defined(CONFIG_PCI)
179/*
180 * Initialize PCI Devices, report devices found.
181 */
182
183#ifndef CONFIG_PCI_PNP
184static struct pci_config_table pci_fsl86xxads_config_table[] = {
185 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
186 PCI_IDSEL_NUMBER, PCI_ANY_ID,
187 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
188 PCI_ENET0_MEMADDR,
189 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
190 {}
191};
192#endif
193
Kumar Gala46f3e382010-07-09 00:02:34 -0500194static struct pci_controller pcie1_hose = {
Joe Hamman8ac27322007-08-09 15:10:53 -0500195#ifndef CONFIG_PCI_PNP
Joe Hammancca34962007-08-11 06:54:58 -0500196 config_table:pci_mpc86xxcts_config_table
Joe Hamman8ac27322007-08-09 15:10:53 -0500197#endif
198};
Joe Hammancca34962007-08-11 06:54:58 -0500199#endif /* CONFIG_PCI */
Joe Hamman8ac27322007-08-09 15:10:53 -0500200
Kumar Gala46f3e382010-07-09 00:02:34 -0500201#ifdef CONFIG_PCIE2
202static struct pci_controller pcie2_hose;
203#endif /* CONFIG_PCIE2 */
Joe Hamman8ac27322007-08-09 15:10:53 -0500204
Joe Hammancca34962007-08-11 06:54:58 -0500205int first_free_busno = 0;
206
207void pci_init_board(void)
Joe Hamman8ac27322007-08-09 15:10:53 -0500208{
Peter Tyser4e339b82010-09-29 13:37:27 -0500209 struct fsl_pci_info pci_info[2];
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
Joe Hammancca34962007-08-11 06:54:58 -0500211 volatile ccsr_gur_t *gur = &immap->im_gur;
Peter Tyser4e339b82010-09-29 13:37:27 -0500212 uint devdisr = in_be32(&gur->devdisr);
Jon Loeliger33fa5c02008-02-25 13:13:37 -0600213 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
214 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
Peter Tyser4e339b82010-09-29 13:37:27 -0500215 int pcie_ep;
216 int num = 0;
Joe Hamman8ac27322007-08-09 15:10:53 -0500217
Kumar Gala46f3e382010-07-09 00:02:34 -0500218#ifdef CONFIG_PCIE1
Peter Tyser4e339b82010-09-29 13:37:27 -0500219 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
Joe Hammancca34962007-08-11 06:54:58 -0500220
Peter Tyser4e339b82010-09-29 13:37:27 -0500221 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
222 SET_STD_PCIE_INFO(pci_info[num], 1);
223 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500224 printf("PCIE1: connected as %s (base addr %lx)\n",
225 pcie_ep ? "Endpoint" : "Root Complex",
226 pci_info[num].regs);
Peter Tyser4e339b82010-09-29 13:37:27 -0500227 first_free_busno = fsl_pci_init_port(&pci_info[num++],
228 &pcie1_hose, first_free_busno);
Joe Hammancca34962007-08-11 06:54:58 -0500229 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500230 puts("PCIE1: disabled\n");
Joe Hammancca34962007-08-11 06:54:58 -0500231 }
Joe Hammancca34962007-08-11 06:54:58 -0500232#else
Peter Tyser8ca78f22010-10-29 17:59:24 -0500233 puts("PCIE1: disabled\n");
Kumar Gala46f3e382010-07-09 00:02:34 -0500234#endif /* CONFIG_PCIE1 */
Joe Hammancca34962007-08-11 06:54:58 -0500235
Kumar Gala46f3e382010-07-09 00:02:34 -0500236#ifdef CONFIG_PCIE2
Joe Hammancca34962007-08-11 06:54:58 -0500237
Peter Tyser4e339b82010-09-29 13:37:27 -0500238 SET_STD_PCIE_INFO(pci_info[num], 2);
239 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500240 printf("PCIE2: connected as %s (base addr %lx)\n",
241 pcie_ep ? "Endpoint" : "Root Complex",
242 pci_info[num].regs);
Peter Tyser4e339b82010-09-29 13:37:27 -0500243 first_free_busno = fsl_pci_init_port(&pci_info[num++],
244 &pcie2_hose, first_free_busno);
Joe Hammancca34962007-08-11 06:54:58 -0500245#else
Peter Tyser8ca78f22010-10-29 17:59:24 -0500246 puts("PCIE2: disabled\n");
Kumar Gala46f3e382010-07-09 00:02:34 -0500247#endif /* CONFIG_PCIE2 */
Joe Hamman8ac27322007-08-09 15:10:53 -0500248}
249
Jon Loeliger13f54332008-02-18 14:01:56 -0600250
251#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Galac2083e02008-10-22 14:38:55 -0500252void ft_board_setup (void *blob, bd_t *bd)
Joe Hamman8ac27322007-08-09 15:10:53 -0500253{
Jon Loeliger13f54332008-02-18 14:01:56 -0600254 ft_cpu_setup(blob, bd);
Joe Hamman8ac27322007-08-09 15:10:53 -0500255
Kumar Gala6525d512010-07-08 22:37:44 -0500256 FT_FSL_PCI_SETUP;
Joe Hamman8ac27322007-08-09 15:10:53 -0500257}
258#endif
259
260void sbc8641d_reset_board (void)
261{
262 puts ("Resetting board....\n");
263}
264
265/*
266 * get_board_sys_clk
267 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
268 */
269
270unsigned long get_board_sys_clk (ulong dummy)
271{
272 int i;
273 ulong val = 0;
274
275 i = 5;
276 i &= 0x07;
277
278 switch (i) {
279 case 0:
280 val = 33000000;
281 break;
282 case 1:
283 val = 40000000;
284 break;
285 case 2:
286 val = 50000000;
287 break;
288 case 3:
289 val = 66000000;
290 break;
291 case 4:
292 val = 83000000;
293 break;
294 case 5:
295 val = 100000000;
296 break;
297 case 6:
298 val = 134000000;
299 break;
300 case 7:
301 val = 166000000;
302 break;
303 }
304
305 return val;
306}
Peter Tyser4ef630d2009-02-05 11:25:25 -0600307
308void board_reset(void)
309{
310#ifdef CONFIG_SYS_RESET_ADDRESS
311 ulong addr = CONFIG_SYS_RESET_ADDRESS;
312
313 /* flush and disable I/D cache */
314 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
315 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
316 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
317 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
318 __asm__ __volatile__ ("sync");
319 __asm__ __volatile__ ("mtspr 1008, 4");
320 __asm__ __volatile__ ("isync");
321 __asm__ __volatile__ ("sync");
322 __asm__ __volatile__ ("mtspr 1008, 5");
323 __asm__ __volatile__ ("isync");
324 __asm__ __volatile__ ("sync");
325
326 /*
327 * SRR0 has system reset vector, SRR1 has default MSR value
328 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
329 */
330 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
331 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
332 __asm__ __volatile__ ("mtspr 27, 4");
333 __asm__ __volatile__ ("rfi");
334#endif
335}
Becky Brucef6ef8b72009-03-31 18:38:37 -0500336
Kumar Gala7649a592009-03-31 23:02:38 -0500337#ifdef CONFIG_MP
Becky Brucef6ef8b72009-03-31 18:38:37 -0500338extern void cpu_mp_lmb_reserve(struct lmb *lmb);
339
340void board_lmb_reserve(struct lmb *lmb)
341{
342 cpu_mp_lmb_reserve(lmb);
343}
344#endif