blob: ad43e8a27cc12404a0b198ece82e0dd8760ea75b [file] [log] [blame]
Simon Glassff3e0772015-03-05 12:25:25 -07001/*
2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
Simon Glassff3e0772015-03-05 12:25:25 -070011#include <inttypes.h>
12#include <pci.h>
Simon Glass21d1fe72015-11-29 13:18:03 -070013#include <asm/io.h>
Simon Glassff3e0772015-03-05 12:25:25 -070014#include <dm/device-internal.h>
Simon Glassbf501592017-05-18 20:09:51 -060015#include <dm/lists.h>
Bin Meng348b7442015-08-20 06:40:23 -070016#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
17#include <asm/fsp/fsp_support.h>
18#endif
Simon Glass5e23b8b2015-11-29 13:17:49 -070019#include "pci_internal.h"
Simon Glassff3e0772015-03-05 12:25:25 -070020
21DECLARE_GLOBAL_DATA_PTR;
22
Simon Glassa6eb93b2016-01-18 20:19:14 -070023int pci_get_bus(int busnum, struct udevice **busp)
Simon Glass983c6ba22015-08-31 18:55:35 -060024{
25 int ret;
26
27 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
28
29 /* Since buses may not be numbered yet try a little harder with bus 0 */
30 if (ret == -ENODEV) {
Simon Glass3f603cb2016-02-11 13:23:26 -070031 ret = uclass_first_device_err(UCLASS_PCI, busp);
Simon Glass983c6ba22015-08-31 18:55:35 -060032 if (ret)
33 return ret;
Simon Glass983c6ba22015-08-31 18:55:35 -060034 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
35 }
36
37 return ret;
38}
39
Simon Glass9f60fb02015-11-19 20:27:00 -070040struct udevice *pci_get_controller(struct udevice *dev)
41{
42 while (device_is_on_pci_bus(dev))
43 dev = dev->parent;
44
45 return dev;
46}
47
Simon Glass21ccce12015-11-29 13:17:47 -070048pci_dev_t dm_pci_get_bdf(struct udevice *dev)
Simon Glass4b515e42015-07-06 16:47:46 -060049{
50 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
51 struct udevice *bus = dev->parent;
52
53 return PCI_ADD_BUS(bus->seq, pplat->devfn);
54}
55
Simon Glassff3e0772015-03-05 12:25:25 -070056/**
57 * pci_get_bus_max() - returns the bus number of the last active bus
58 *
59 * @return last bus number, or -1 if no active buses
60 */
61static int pci_get_bus_max(void)
62{
63 struct udevice *bus;
64 struct uclass *uc;
65 int ret = -1;
66
67 ret = uclass_get(UCLASS_PCI, &uc);
68 uclass_foreach_dev(bus, uc) {
69 if (bus->seq > ret)
70 ret = bus->seq;
71 }
72
73 debug("%s: ret=%d\n", __func__, ret);
74
75 return ret;
76}
77
78int pci_last_busno(void)
79{
Bin Meng069155c2015-10-01 00:36:01 -070080 return pci_get_bus_max();
Simon Glassff3e0772015-03-05 12:25:25 -070081}
82
83int pci_get_ff(enum pci_size_t size)
84{
85 switch (size) {
86 case PCI_SIZE_8:
87 return 0xff;
88 case PCI_SIZE_16:
89 return 0xffff;
90 default:
91 return 0xffffffff;
92 }
93}
94
95int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
96 struct udevice **devp)
97{
98 struct udevice *dev;
99
100 for (device_find_first_child(bus, &dev);
101 dev;
102 device_find_next_child(&dev)) {
103 struct pci_child_platdata *pplat;
104
105 pplat = dev_get_parent_platdata(dev);
106 if (pplat && pplat->devfn == find_devfn) {
107 *devp = dev;
108 return 0;
109 }
110 }
111
112 return -ENODEV;
113}
114
Simon Glassf3f1fae2015-11-29 13:17:48 -0700115int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
Simon Glassff3e0772015-03-05 12:25:25 -0700116{
117 struct udevice *bus;
118 int ret;
119
Simon Glass983c6ba22015-08-31 18:55:35 -0600120 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700121 if (ret)
122 return ret;
123 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
124}
125
126static int pci_device_matches_ids(struct udevice *dev,
127 struct pci_device_id *ids)
128{
129 struct pci_child_platdata *pplat;
130 int i;
131
132 pplat = dev_get_parent_platdata(dev);
133 if (!pplat)
134 return -EINVAL;
135 for (i = 0; ids[i].vendor != 0; i++) {
136 if (pplat->vendor == ids[i].vendor &&
137 pplat->device == ids[i].device)
138 return i;
139 }
140
141 return -EINVAL;
142}
143
144int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
145 int *indexp, struct udevice **devp)
146{
147 struct udevice *dev;
148
149 /* Scan all devices on this bus */
150 for (device_find_first_child(bus, &dev);
151 dev;
152 device_find_next_child(&dev)) {
153 if (pci_device_matches_ids(dev, ids) >= 0) {
154 if ((*indexp)-- <= 0) {
155 *devp = dev;
156 return 0;
157 }
158 }
159 }
160
161 return -ENODEV;
162}
163
164int pci_find_device_id(struct pci_device_id *ids, int index,
165 struct udevice **devp)
166{
167 struct udevice *bus;
168
169 /* Scan all known buses */
170 for (uclass_first_device(UCLASS_PCI, &bus);
171 bus;
172 uclass_next_device(&bus)) {
173 if (!pci_bus_find_devices(bus, ids, &index, devp))
174 return 0;
175 }
176 *devp = NULL;
177
178 return -ENODEV;
179}
180
Simon Glass5c0bf642015-11-29 13:17:50 -0700181static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
182 unsigned int device, int *indexp,
183 struct udevice **devp)
184{
185 struct pci_child_platdata *pplat;
186 struct udevice *dev;
187
188 for (device_find_first_child(bus, &dev);
189 dev;
190 device_find_next_child(&dev)) {
191 pplat = dev_get_parent_platdata(dev);
192 if (pplat->vendor == vendor && pplat->device == device) {
193 if (!(*indexp)--) {
194 *devp = dev;
195 return 0;
196 }
197 }
198 }
199
200 return -ENODEV;
201}
202
203int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
204 struct udevice **devp)
205{
206 struct udevice *bus;
207
208 /* Scan all known buses */
209 for (uclass_first_device(UCLASS_PCI, &bus);
210 bus;
211 uclass_next_device(&bus)) {
212 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
213 return device_probe(*devp);
214 }
215 *devp = NULL;
216
217 return -ENODEV;
218}
219
Simon Glassa0eb8352015-11-29 13:17:52 -0700220int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
221{
222 struct udevice *dev;
223
224 /* Scan all known buses */
225 for (pci_find_first_device(&dev);
226 dev;
227 pci_find_next_device(&dev)) {
228 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
229
230 if (pplat->class == find_class && !index--) {
231 *devp = dev;
232 return device_probe(*devp);
233 }
234 }
235 *devp = NULL;
236
237 return -ENODEV;
238}
239
Simon Glassff3e0772015-03-05 12:25:25 -0700240int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
241 unsigned long value, enum pci_size_t size)
242{
243 struct dm_pci_ops *ops;
244
245 ops = pci_get_ops(bus);
246 if (!ops->write_config)
247 return -ENOSYS;
248 return ops->write_config(bus, bdf, offset, value, size);
249}
250
Simon Glass319dba12016-03-06 19:27:52 -0700251int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
252 u32 clr, u32 set)
253{
254 ulong val;
255 int ret;
256
257 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
258 if (ret)
259 return ret;
260 val &= ~clr;
261 val |= set;
262
263 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
264}
265
Simon Glassff3e0772015-03-05 12:25:25 -0700266int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
267 enum pci_size_t size)
268{
269 struct udevice *bus;
270 int ret;
271
Simon Glass983c6ba22015-08-31 18:55:35 -0600272 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700273 if (ret)
274 return ret;
275
Bin Meng4d8615c2015-07-19 00:20:04 +0800276 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700277}
278
Simon Glass66afb4e2015-08-10 07:05:03 -0600279int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
280 enum pci_size_t size)
281{
282 struct udevice *bus;
283
Bin Meng1e0f2262015-09-11 03:24:34 -0700284 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600285 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700286 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
287 size);
Simon Glass66afb4e2015-08-10 07:05:03 -0600288}
289
Simon Glassff3e0772015-03-05 12:25:25 -0700290int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
291{
292 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
293}
294
295int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
296{
297 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
298}
299
300int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
301{
302 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
303}
304
Simon Glass66afb4e2015-08-10 07:05:03 -0600305int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
306{
307 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
308}
309
310int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
311{
312 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
313}
314
315int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
316{
317 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
318}
319
Simon Glassff3e0772015-03-05 12:25:25 -0700320int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
321 unsigned long *valuep, enum pci_size_t size)
322{
323 struct dm_pci_ops *ops;
324
325 ops = pci_get_ops(bus);
326 if (!ops->read_config)
327 return -ENOSYS;
328 return ops->read_config(bus, bdf, offset, valuep, size);
329}
330
331int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
332 enum pci_size_t size)
333{
334 struct udevice *bus;
335 int ret;
336
Simon Glass983c6ba22015-08-31 18:55:35 -0600337 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700338 if (ret)
339 return ret;
340
Bin Meng4d8615c2015-07-19 00:20:04 +0800341 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700342}
343
Simon Glass66afb4e2015-08-10 07:05:03 -0600344int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
345 enum pci_size_t size)
346{
347 struct udevice *bus;
348
Bin Meng1e0f2262015-09-11 03:24:34 -0700349 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600350 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700351 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
Simon Glass66afb4e2015-08-10 07:05:03 -0600352 size);
353}
354
Simon Glassff3e0772015-03-05 12:25:25 -0700355int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
356{
357 unsigned long value;
358 int ret;
359
360 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
361 if (ret)
362 return ret;
363 *valuep = value;
364
365 return 0;
366}
367
368int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
369{
370 unsigned long value;
371 int ret;
372
373 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
374 if (ret)
375 return ret;
376 *valuep = value;
377
378 return 0;
379}
380
381int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
382{
383 unsigned long value;
384 int ret;
385
386 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
387 if (ret)
388 return ret;
389 *valuep = value;
390
391 return 0;
392}
393
Simon Glass66afb4e2015-08-10 07:05:03 -0600394int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
395{
396 unsigned long value;
397 int ret;
398
399 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
400 if (ret)
401 return ret;
402 *valuep = value;
403
404 return 0;
405}
406
407int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
408{
409 unsigned long value;
410 int ret;
411
412 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
413 if (ret)
414 return ret;
415 *valuep = value;
416
417 return 0;
418}
419
420int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
421{
422 unsigned long value;
423 int ret;
424
425 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
426 if (ret)
427 return ret;
428 *valuep = value;
429
430 return 0;
431}
432
Simon Glass319dba12016-03-06 19:27:52 -0700433int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
434{
435 u8 val;
436 int ret;
437
438 ret = dm_pci_read_config8(dev, offset, &val);
439 if (ret)
440 return ret;
441 val &= ~clr;
442 val |= set;
443
444 return dm_pci_write_config8(dev, offset, val);
445}
446
447int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
448{
449 u16 val;
450 int ret;
451
452 ret = dm_pci_read_config16(dev, offset, &val);
453 if (ret)
454 return ret;
455 val &= ~clr;
456 val |= set;
457
458 return dm_pci_write_config16(dev, offset, val);
459}
460
461int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
462{
463 u32 val;
464 int ret;
465
466 ret = dm_pci_read_config32(dev, offset, &val);
467 if (ret)
468 return ret;
469 val &= ~clr;
470 val |= set;
471
472 return dm_pci_write_config32(dev, offset, val);
473}
474
Bin Mengbbbcb522015-10-01 00:36:02 -0700475static void set_vga_bridge_bits(struct udevice *dev)
476{
477 struct udevice *parent = dev->parent;
478 u16 bc;
479
480 while (parent->seq != 0) {
481 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
482 bc |= PCI_BRIDGE_CTL_VGA;
483 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
484 parent = parent->parent;
485 }
486}
487
Simon Glassff3e0772015-03-05 12:25:25 -0700488int pci_auto_config_devices(struct udevice *bus)
489{
490 struct pci_controller *hose = bus->uclass_priv;
Bin Mengbbbcb522015-10-01 00:36:02 -0700491 struct pci_child_platdata *pplat;
Simon Glassff3e0772015-03-05 12:25:25 -0700492 unsigned int sub_bus;
493 struct udevice *dev;
494 int ret;
495
496 sub_bus = bus->seq;
497 debug("%s: start\n", __func__);
498 pciauto_config_init(hose);
499 for (ret = device_find_first_child(bus, &dev);
500 !ret && dev;
501 ret = device_find_next_child(&dev)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700502 unsigned int max_bus;
Simon Glass4d214552015-09-08 17:52:47 -0600503 int ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700504
Simon Glassff3e0772015-03-05 12:25:25 -0700505 debug("%s: device %s\n", __func__, dev->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700506 ret = dm_pciauto_config_device(dev);
Simon Glass4d214552015-09-08 17:52:47 -0600507 if (ret < 0)
508 return ret;
509 max_bus = ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700510 sub_bus = max(sub_bus, max_bus);
Bin Mengbbbcb522015-10-01 00:36:02 -0700511
512 pplat = dev_get_parent_platdata(dev);
513 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
514 set_vga_bridge_bits(dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700515 }
516 debug("%s: done\n", __func__);
517
518 return sub_bus;
519}
520
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +0300521int pci_generic_mmap_write_config(
522 struct udevice *bus,
523 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
524 pci_dev_t bdf,
525 uint offset,
526 ulong value,
527 enum pci_size_t size)
528{
529 void *address;
530
531 if (addr_f(bus, bdf, offset, &address) < 0)
532 return 0;
533
534 switch (size) {
535 case PCI_SIZE_8:
536 writeb(value, address);
537 return 0;
538 case PCI_SIZE_16:
539 writew(value, address);
540 return 0;
541 case PCI_SIZE_32:
542 writel(value, address);
543 return 0;
544 default:
545 return -EINVAL;
546 }
547}
548
549int pci_generic_mmap_read_config(
550 struct udevice *bus,
551 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
552 pci_dev_t bdf,
553 uint offset,
554 ulong *valuep,
555 enum pci_size_t size)
556{
557 void *address;
558
559 if (addr_f(bus, bdf, offset, &address) < 0) {
560 *valuep = pci_get_ff(size);
561 return 0;
562 }
563
564 switch (size) {
565 case PCI_SIZE_8:
566 *valuep = readb(address);
567 return 0;
568 case PCI_SIZE_16:
569 *valuep = readw(address);
570 return 0;
571 case PCI_SIZE_32:
572 *valuep = readl(address);
573 return 0;
574 default:
575 return -EINVAL;
576 }
577}
578
Simon Glass5e23b8b2015-11-29 13:17:49 -0700579int dm_pci_hose_probe_bus(struct udevice *bus)
Simon Glassff3e0772015-03-05 12:25:25 -0700580{
Simon Glassff3e0772015-03-05 12:25:25 -0700581 int sub_bus;
582 int ret;
583
584 debug("%s\n", __func__);
Simon Glassff3e0772015-03-05 12:25:25 -0700585
586 sub_bus = pci_get_bus_max() + 1;
587 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700588 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700589
590 ret = device_probe(bus);
591 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600592 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassff3e0772015-03-05 12:25:25 -0700593 ret);
594 return ret;
595 }
596 if (sub_bus != bus->seq) {
597 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
598 __func__, bus->name, bus->seq, sub_bus);
599 return -EPIPE;
600 }
601 sub_bus = pci_get_bus_max();
Simon Glass5e23b8b2015-11-29 13:17:49 -0700602 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700603
604 return sub_bus;
605}
606
Simon Glassaba92962015-07-06 16:47:44 -0600607/**
608 * pci_match_one_device - Tell if a PCI device structure has a matching
609 * PCI device id structure
610 * @id: single PCI device id structure to match
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800611 * @find: the PCI device id structure to match against
Simon Glassaba92962015-07-06 16:47:44 -0600612 *
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800613 * Returns true if the finding pci_device_id structure matched or false if
614 * there is no match.
Simon Glassaba92962015-07-06 16:47:44 -0600615 */
616static bool pci_match_one_id(const struct pci_device_id *id,
617 const struct pci_device_id *find)
618{
619 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
620 (id->device == PCI_ANY_ID || id->device == find->device) &&
621 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
622 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
623 !((id->class ^ find->class) & id->class_mask))
624 return true;
625
626 return false;
627}
628
629/**
630 * pci_find_and_bind_driver() - Find and bind the right PCI driver
631 *
632 * This only looks at certain fields in the descriptor.
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600633 *
634 * @parent: Parent bus
635 * @find_id: Specification of the driver to find
636 * @bdf: Bus/device/function addreess - see PCI_BDF()
637 * @devp: Returns a pointer to the device created
638 * @return 0 if OK, -EPERM if the device is not needed before relocation and
639 * therefore was not created, other -ve value on error
Simon Glassaba92962015-07-06 16:47:44 -0600640 */
641static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600642 struct pci_device_id *find_id,
643 pci_dev_t bdf, struct udevice **devp)
Simon Glassaba92962015-07-06 16:47:44 -0600644{
645 struct pci_driver_entry *start, *entry;
646 const char *drv;
647 int n_ents;
648 int ret;
649 char name[30], *str;
Bin Meng08fc7b82015-08-20 06:40:17 -0700650 bool bridge;
Simon Glassaba92962015-07-06 16:47:44 -0600651
652 *devp = NULL;
653
654 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
655 find_id->vendor, find_id->device);
656 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
657 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
658 for (entry = start; entry != start + n_ents; entry++) {
659 const struct pci_device_id *id;
660 struct udevice *dev;
661 const struct driver *drv;
662
663 for (id = entry->match;
664 id->vendor || id->subvendor || id->class_mask;
665 id++) {
666 if (!pci_match_one_id(id, find_id))
667 continue;
668
669 drv = entry->driver;
Bin Meng08fc7b82015-08-20 06:40:17 -0700670
671 /*
672 * In the pre-relocation phase, we only bind devices
673 * whose driver has the DM_FLAG_PRE_RELOC set, to save
674 * precious memory space as on some platforms as that
675 * space is pretty limited (ie: using Cache As RAM).
676 */
677 if (!(gd->flags & GD_FLG_RELOC) &&
678 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600679 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700680
Simon Glassaba92962015-07-06 16:47:44 -0600681 /*
682 * We could pass the descriptor to the driver as
683 * platdata (instead of NULL) and allow its bind()
684 * method to return -ENOENT if it doesn't support this
685 * device. That way we could continue the search to
686 * find another driver. For now this doesn't seem
687 * necesssary, so just bind the first match.
688 */
689 ret = device_bind(parent, drv, drv->name, NULL, -1,
690 &dev);
691 if (ret)
692 goto error;
693 debug("%s: Match found: %s\n", __func__, drv->name);
694 dev->driver_data = find_id->driver_data;
695 *devp = dev;
696 return 0;
697 }
698 }
699
Bin Meng08fc7b82015-08-20 06:40:17 -0700700 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
701 /*
702 * In the pre-relocation phase, we only bind bridge devices to save
703 * precious memory space as on some platforms as that space is pretty
704 * limited (ie: using Cache As RAM).
705 */
706 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600707 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700708
Simon Glassaba92962015-07-06 16:47:44 -0600709 /* Bind a generic driver so that the device can be used */
Bin Meng4d8615c2015-07-19 00:20:04 +0800710 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
711 PCI_FUNC(bdf));
Simon Glassaba92962015-07-06 16:47:44 -0600712 str = strdup(name);
713 if (!str)
714 return -ENOMEM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700715 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
716
Simon Glassaba92962015-07-06 16:47:44 -0600717 ret = device_bind_driver(parent, drv, str, devp);
718 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600719 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
xypron.glpk@gmx.dec42640c2017-05-08 20:40:16 +0200720 free(str);
Simon Glassaba92962015-07-06 16:47:44 -0600721 return ret;
722 }
723 debug("%s: No match found: bound generic driver instead\n", __func__);
724
725 return 0;
726
727error:
728 debug("%s: No match found: error %d\n", __func__, ret);
729 return ret;
730}
731
Simon Glassff3e0772015-03-05 12:25:25 -0700732int pci_bind_bus_devices(struct udevice *bus)
733{
734 ulong vendor, device;
735 ulong header_type;
Bin Meng4d8615c2015-07-19 00:20:04 +0800736 pci_dev_t bdf, end;
Simon Glassff3e0772015-03-05 12:25:25 -0700737 bool found_multi;
738 int ret;
739
740 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800741 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
742 PCI_MAX_PCI_FUNCTIONS - 1);
Yoshinori Sato6d9f5b02016-04-25 15:41:01 +0900743 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
Bin Meng4d8615c2015-07-19 00:20:04 +0800744 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700745 struct pci_child_platdata *pplat;
746 struct udevice *dev;
747 ulong class;
748
Bin Meng4d8615c2015-07-19 00:20:04 +0800749 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassff3e0772015-03-05 12:25:25 -0700750 continue;
751 /* Check only the first access, we don't expect problems */
Bin Meng4d8615c2015-07-19 00:20:04 +0800752 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
Simon Glassff3e0772015-03-05 12:25:25 -0700753 &header_type, PCI_SIZE_8);
754 if (ret)
755 goto error;
Bin Meng4d8615c2015-07-19 00:20:04 +0800756 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
Simon Glassff3e0772015-03-05 12:25:25 -0700757 PCI_SIZE_16);
758 if (vendor == 0xffff || vendor == 0x0000)
759 continue;
760
Bin Meng4d8615c2015-07-19 00:20:04 +0800761 if (!PCI_FUNC(bdf))
Simon Glassff3e0772015-03-05 12:25:25 -0700762 found_multi = header_type & 0x80;
763
764 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
Bin Meng4d8615c2015-07-19 00:20:04 +0800765 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
766 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassff3e0772015-03-05 12:25:25 -0700767 PCI_SIZE_16);
Bin Meng4d8615c2015-07-19 00:20:04 +0800768 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glassaba92962015-07-06 16:47:44 -0600769 PCI_SIZE_32);
770 class >>= 8;
Simon Glassff3e0772015-03-05 12:25:25 -0700771
772 /* Find this device in the device tree */
Bin Meng4d8615c2015-07-19 00:20:04 +0800773 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700774
Simon Glass8bd42522015-11-29 13:18:09 -0700775 /* If nothing in the device tree, bind a device */
Simon Glassff3e0772015-03-05 12:25:25 -0700776 if (ret == -ENODEV) {
Simon Glassaba92962015-07-06 16:47:44 -0600777 struct pci_device_id find_id;
778 ulong val;
Simon Glassff3e0772015-03-05 12:25:25 -0700779
Simon Glassaba92962015-07-06 16:47:44 -0600780 memset(&find_id, '\0', sizeof(find_id));
781 find_id.vendor = vendor;
782 find_id.device = device;
783 find_id.class = class;
784 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng4d8615c2015-07-19 00:20:04 +0800785 pci_bus_read_config(bus, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600786 PCI_SUBSYSTEM_VENDOR_ID,
787 &val, PCI_SIZE_32);
788 find_id.subvendor = val & 0xffff;
789 find_id.subdevice = val >> 16;
790 }
Bin Meng4d8615c2015-07-19 00:20:04 +0800791 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600792 &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700793 }
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600794 if (ret == -EPERM)
795 continue;
796 else if (ret)
Simon Glassff3e0772015-03-05 12:25:25 -0700797 return ret;
798
799 /* Update the platform data */
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600800 pplat = dev_get_parent_platdata(dev);
801 pplat->devfn = PCI_MASK_BUS(bdf);
802 pplat->vendor = vendor;
803 pplat->device = device;
804 pplat->class = class;
Simon Glassff3e0772015-03-05 12:25:25 -0700805 }
806
807 return 0;
808error:
809 printf("Cannot read bus configuration: %d\n", ret);
810
811 return ret;
812}
813
Simon Glassbf501592017-05-18 20:09:51 -0600814static int decode_regions(struct pci_controller *hose, ofnode parent_node,
815 ofnode node)
Simon Glassff3e0772015-03-05 12:25:25 -0700816{
817 int pci_addr_cells, addr_cells, size_cells;
818 int cells_per_record;
819 const u32 *prop;
820 int len;
821 int i;
822
Masahiro Yamada61e51ba2017-06-22 16:54:05 +0900823 prop = ofnode_get_property(node, "ranges", &len);
Simon Glassff3e0772015-03-05 12:25:25 -0700824 if (!prop)
825 return -EINVAL;
Simon Glass878d68c2017-06-12 06:21:31 -0600826 pci_addr_cells = ofnode_read_simple_addr_cells(node);
827 addr_cells = ofnode_read_simple_addr_cells(parent_node);
828 size_cells = ofnode_read_simple_size_cells(node);
Simon Glassff3e0772015-03-05 12:25:25 -0700829
830 /* PCI addresses are always 3-cells */
831 len /= sizeof(u32);
832 cells_per_record = pci_addr_cells + addr_cells + size_cells;
833 hose->region_count = 0;
834 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
835 cells_per_record);
836 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
837 u64 pci_addr, addr, size;
838 int space_code;
839 u32 flags;
840 int type;
Simon Glass9526d832015-11-19 20:26:58 -0700841 int pos;
Simon Glassff3e0772015-03-05 12:25:25 -0700842
843 if (len < cells_per_record)
844 break;
845 flags = fdt32_to_cpu(prop[0]);
846 space_code = (flags >> 24) & 3;
847 pci_addr = fdtdec_get_number(prop + 1, 2);
848 prop += pci_addr_cells;
849 addr = fdtdec_get_number(prop, addr_cells);
850 prop += addr_cells;
851 size = fdtdec_get_number(prop, size_cells);
852 prop += size_cells;
853 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
854 ", size=%" PRIx64 ", space_code=%d\n", __func__,
855 hose->region_count, pci_addr, addr, size, space_code);
856 if (space_code & 2) {
857 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
858 PCI_REGION_MEM;
859 } else if (space_code & 1) {
860 type = PCI_REGION_IO;
861 } else {
862 continue;
863 }
Simon Glass9526d832015-11-19 20:26:58 -0700864 pos = -1;
865 for (i = 0; i < hose->region_count; i++) {
866 if (hose->regions[i].flags == type)
867 pos = i;
868 }
869 if (pos == -1)
870 pos = hose->region_count++;
871 debug(" - type=%d, pos=%d\n", type, pos);
872 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassff3e0772015-03-05 12:25:25 -0700873 }
874
875 /* Add a region for our local memory */
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100876#ifdef CONFIG_NR_DRAM_BANKS
877 bd_t *bd = gd->bd;
878
879 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
880 if (bd->bi_dram[i].size) {
881 pci_set_region(hose->regions + hose->region_count++,
882 bd->bi_dram[i].start,
883 bd->bi_dram[i].start,
884 bd->bi_dram[i].size,
885 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
886 }
887 }
888#else
889 phys_addr_t base = 0, size;
890
Simon Glass2084c5a2015-11-19 20:26:57 -0700891 size = gd->ram_size;
892#ifdef CONFIG_SYS_SDRAM_BASE
893 base = CONFIG_SYS_SDRAM_BASE;
894#endif
895 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
896 size = gd->pci_ram_top - base;
897 pci_set_region(hose->regions + hose->region_count++, base, base,
898 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100899#endif
Simon Glassff3e0772015-03-05 12:25:25 -0700900
901 return 0;
902}
903
904static int pci_uclass_pre_probe(struct udevice *bus)
905{
906 struct pci_controller *hose;
907 int ret;
908
909 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
910 bus->parent->name);
911 hose = bus->uclass_priv;
912
913 /* For bridges, use the top-level PCI controller */
Paul Burton65f62b12016-09-08 07:47:32 +0100914 if (!device_is_on_pci_bus(bus)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700915 hose->ctlr = bus;
Simon Glassbf501592017-05-18 20:09:51 -0600916 ret = decode_regions(hose, dev_ofnode(bus->parent),
917 dev_ofnode(bus));
Simon Glassff3e0772015-03-05 12:25:25 -0700918 if (ret) {
919 debug("%s: Cannot decode regions\n", __func__);
920 return ret;
921 }
922 } else {
923 struct pci_controller *parent_hose;
924
925 parent_hose = dev_get_uclass_priv(bus->parent);
926 hose->ctlr = parent_hose->bus;
927 }
928 hose->bus = bus;
929 hose->first_busno = bus->seq;
930 hose->last_busno = bus->seq;
931
932 return 0;
933}
934
935static int pci_uclass_post_probe(struct udevice *bus)
936{
937 int ret;
938
Simon Glassff3e0772015-03-05 12:25:25 -0700939 debug("%s: probing bus %d\n", __func__, bus->seq);
940 ret = pci_bind_bus_devices(bus);
941 if (ret)
942 return ret;
943
944#ifdef CONFIG_PCI_PNP
945 ret = pci_auto_config_devices(bus);
Simon Glass4d214552015-09-08 17:52:47 -0600946 if (ret < 0)
947 return ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700948#endif
949
Bin Meng348b7442015-08-20 06:40:23 -0700950#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
951 /*
952 * Per Intel FSP specification, we should call FSP notify API to
953 * inform FSP that PCI enumeration has been done so that FSP will
954 * do any necessary initialization as required by the chipset's
955 * BIOS Writer's Guide (BWG).
956 *
957 * Unfortunately we have to put this call here as with driver model,
958 * the enumeration is all done on a lazy basis as needed, so until
959 * something is touched on PCI it won't happen.
960 *
961 * Note we only call this 1) after U-Boot is relocated, and 2)
962 * root bus has finished probing.
963 */
Simon Glass4d214552015-09-08 17:52:47 -0600964 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
Bin Meng348b7442015-08-20 06:40:23 -0700965 ret = fsp_init_phase_pci();
Simon Glass4d214552015-09-08 17:52:47 -0600966 if (ret)
967 return ret;
968 }
Bin Meng348b7442015-08-20 06:40:23 -0700969#endif
970
Simon Glass4d214552015-09-08 17:52:47 -0600971 return 0;
Simon Glassff3e0772015-03-05 12:25:25 -0700972}
973
974static int pci_uclass_child_post_bind(struct udevice *dev)
975{
976 struct pci_child_platdata *pplat;
977 struct fdt_pci_addr addr;
978 int ret;
979
Simon Glassbf501592017-05-18 20:09:51 -0600980 if (!dev_of_valid(dev))
Simon Glassff3e0772015-03-05 12:25:25 -0700981 return 0;
982
983 /*
984 * We could read vendor, device, class if available. But for now we
985 * just check the address.
986 */
987 pplat = dev_get_parent_platdata(dev);
Simon Glassbf501592017-05-18 20:09:51 -0600988 ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
989 &addr);
Simon Glassff3e0772015-03-05 12:25:25 -0700990
991 if (ret) {
992 if (ret != -ENOENT)
993 return -EINVAL;
994 } else {
Bin Mengdce54dd2015-08-20 06:40:26 -0700995 /* extract the devfn from fdt_pci_addr */
996 pplat->devfn = addr.phys_hi & 0xff00;
Simon Glassff3e0772015-03-05 12:25:25 -0700997 }
998
999 return 0;
1000}
1001
Bin Meng4d8615c2015-07-19 00:20:04 +08001002static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
1003 uint offset, ulong *valuep,
1004 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001005{
1006 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001007
1008 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1009}
1010
Bin Meng4d8615c2015-07-19 00:20:04 +08001011static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1012 uint offset, ulong value,
1013 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001014{
1015 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001016
1017 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1018}
1019
Simon Glass76c3fbc2015-08-10 07:05:04 -06001020static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1021{
1022 struct udevice *dev;
1023 int ret = 0;
1024
1025 /*
1026 * Scan through all the PCI controllers. On x86 there will only be one
1027 * but that is not necessarily true on other hardware.
1028 */
1029 do {
1030 device_find_first_child(bus, &dev);
1031 if (dev) {
1032 *devp = dev;
1033 return 0;
1034 }
1035 ret = uclass_next_device(&bus);
1036 if (ret)
1037 return ret;
1038 } while (bus);
1039
1040 return 0;
1041}
1042
1043int pci_find_next_device(struct udevice **devp)
1044{
1045 struct udevice *child = *devp;
1046 struct udevice *bus = child->parent;
1047 int ret;
1048
1049 /* First try all the siblings */
1050 *devp = NULL;
1051 while (child) {
1052 device_find_next_child(&child);
1053 if (child) {
1054 *devp = child;
1055 return 0;
1056 }
1057 }
1058
1059 /* We ran out of siblings. Try the next bus */
1060 ret = uclass_next_device(&bus);
1061 if (ret)
1062 return ret;
1063
1064 return bus ? skip_to_next_device(bus, devp) : 0;
1065}
1066
1067int pci_find_first_device(struct udevice **devp)
1068{
1069 struct udevice *bus;
1070 int ret;
1071
1072 *devp = NULL;
1073 ret = uclass_first_device(UCLASS_PCI, &bus);
1074 if (ret)
1075 return ret;
1076
1077 return skip_to_next_device(bus, devp);
1078}
1079
Simon Glass9289db62015-11-19 20:26:59 -07001080ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1081{
1082 switch (size) {
1083 case PCI_SIZE_8:
1084 return (value >> ((offset & 3) * 8)) & 0xff;
1085 case PCI_SIZE_16:
1086 return (value >> ((offset & 2) * 8)) & 0xffff;
1087 default:
1088 return value;
1089 }
1090}
1091
1092ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1093 enum pci_size_t size)
1094{
1095 uint off_mask;
1096 uint val_mask, shift;
1097 ulong ldata, mask;
1098
1099 switch (size) {
1100 case PCI_SIZE_8:
1101 off_mask = 3;
1102 val_mask = 0xff;
1103 break;
1104 case PCI_SIZE_16:
1105 off_mask = 2;
1106 val_mask = 0xffff;
1107 break;
1108 default:
1109 return value;
1110 }
1111 shift = (offset & off_mask) * 8;
1112 ldata = (value & val_mask) << shift;
1113 mask = val_mask << shift;
1114 value = (old & ~mask) | ldata;
1115
1116 return value;
1117}
1118
Simon Glassf9260332015-11-19 20:27:01 -07001119int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1120 struct pci_region **memp, struct pci_region **prefp)
1121{
1122 struct udevice *bus = pci_get_controller(dev);
1123 struct pci_controller *hose = dev_get_uclass_priv(bus);
1124 int i;
1125
1126 *iop = NULL;
1127 *memp = NULL;
1128 *prefp = NULL;
1129 for (i = 0; i < hose->region_count; i++) {
1130 switch (hose->regions[i].flags) {
1131 case PCI_REGION_IO:
1132 if (!*iop || (*iop)->size < hose->regions[i].size)
1133 *iop = hose->regions + i;
1134 break;
1135 case PCI_REGION_MEM:
1136 if (!*memp || (*memp)->size < hose->regions[i].size)
1137 *memp = hose->regions + i;
1138 break;
1139 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1140 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1141 *prefp = hose->regions + i;
1142 break;
1143 }
1144 }
1145
1146 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1147}
1148
Simon Glassbab17cf2015-11-29 13:17:53 -07001149u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1150{
1151 u32 addr;
1152 int bar;
1153
1154 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1155 dm_pci_read_config32(dev, bar, &addr);
1156 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1157 return addr & PCI_BASE_ADDRESS_IO_MASK;
1158 else
1159 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1160}
1161
Simon Glass9d731c82016-01-18 20:19:15 -07001162void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1163{
1164 int bar;
1165
1166 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1167 dm_pci_write_config32(dev, bar, addr);
1168}
1169
Simon Glass21d1fe72015-11-29 13:18:03 -07001170static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1171 pci_addr_t bus_addr, unsigned long flags,
1172 unsigned long skip_mask, phys_addr_t *pa)
1173{
1174 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1175 struct pci_region *res;
1176 int i;
1177
1178 for (i = 0; i < hose->region_count; i++) {
1179 res = &hose->regions[i];
1180
1181 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1182 continue;
1183
1184 if (res->flags & skip_mask)
1185 continue;
1186
1187 if (bus_addr >= res->bus_start &&
1188 (bus_addr - res->bus_start) < res->size) {
1189 *pa = (bus_addr - res->bus_start + res->phys_start);
1190 return 0;
1191 }
1192 }
1193
1194 return 1;
1195}
1196
1197phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1198 unsigned long flags)
1199{
1200 phys_addr_t phys_addr = 0;
1201 struct udevice *ctlr;
1202 int ret;
1203
1204 /* The root controller has the region information */
1205 ctlr = pci_get_controller(dev);
1206
1207 /*
1208 * if PCI_REGION_MEM is set we do a two pass search with preference
1209 * on matches that don't have PCI_REGION_SYS_MEMORY set
1210 */
1211 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1212 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1213 flags, PCI_REGION_SYS_MEMORY,
1214 &phys_addr);
1215 if (!ret)
1216 return phys_addr;
1217 }
1218
1219 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1220
1221 if (ret)
1222 puts("pci_hose_bus_to_phys: invalid physical address\n");
1223
1224 return phys_addr;
1225}
1226
1227int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1228 unsigned long flags, unsigned long skip_mask,
1229 pci_addr_t *ba)
1230{
1231 struct pci_region *res;
1232 struct udevice *ctlr;
1233 pci_addr_t bus_addr;
1234 int i;
1235 struct pci_controller *hose;
1236
1237 /* The root controller has the region information */
1238 ctlr = pci_get_controller(dev);
1239 hose = dev_get_uclass_priv(ctlr);
1240
1241 for (i = 0; i < hose->region_count; i++) {
1242 res = &hose->regions[i];
1243
1244 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1245 continue;
1246
1247 if (res->flags & skip_mask)
1248 continue;
1249
1250 bus_addr = phys_addr - res->phys_start + res->bus_start;
1251
1252 if (bus_addr >= res->bus_start &&
1253 (bus_addr - res->bus_start) < res->size) {
1254 *ba = bus_addr;
1255 return 0;
1256 }
1257 }
1258
1259 return 1;
1260}
1261
1262pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1263 unsigned long flags)
1264{
1265 pci_addr_t bus_addr = 0;
1266 int ret;
1267
1268 /*
1269 * if PCI_REGION_MEM is set we do a two pass search with preference
1270 * on matches that don't have PCI_REGION_SYS_MEMORY set
1271 */
1272 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1273 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1274 PCI_REGION_SYS_MEMORY, &bus_addr);
1275 if (!ret)
1276 return bus_addr;
1277 }
1278
1279 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1280
1281 if (ret)
1282 puts("pci_hose_phys_to_bus: invalid physical address\n");
1283
1284 return bus_addr;
1285}
1286
1287void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1288{
1289 pci_addr_t pci_bus_addr;
1290 u32 bar_response;
1291
1292 /* read BAR address */
1293 dm_pci_read_config32(dev, bar, &bar_response);
1294 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1295
1296 /*
1297 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1298 * isn't actualy used on any platform because u-boot assumes a static
1299 * linear mapping. In the future, this could read the BAR size
1300 * and pass that as the size if needed.
1301 */
1302 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1303}
1304
Simon Glassff3e0772015-03-05 12:25:25 -07001305UCLASS_DRIVER(pci) = {
1306 .id = UCLASS_PCI,
1307 .name = "pci",
Simon Glass2bb02e42015-05-10 21:08:06 -06001308 .flags = DM_UC_FLAG_SEQ_ALIAS,
Simon Glass91195482016-07-05 17:10:10 -06001309 .post_bind = dm_scan_fdt_dev,
Simon Glassff3e0772015-03-05 12:25:25 -07001310 .pre_probe = pci_uclass_pre_probe,
1311 .post_probe = pci_uclass_post_probe,
1312 .child_post_bind = pci_uclass_child_post_bind,
1313 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1314 .per_child_platdata_auto_alloc_size =
1315 sizeof(struct pci_child_platdata),
1316};
1317
1318static const struct dm_pci_ops pci_bridge_ops = {
1319 .read_config = pci_bridge_read_config,
1320 .write_config = pci_bridge_write_config,
1321};
1322
1323static const struct udevice_id pci_bridge_ids[] = {
1324 { .compatible = "pci-bridge" },
1325 { }
1326};
1327
1328U_BOOT_DRIVER(pci_bridge_drv) = {
1329 .name = "pci_bridge_drv",
1330 .id = UCLASS_PCI,
1331 .of_match = pci_bridge_ids,
1332 .ops = &pci_bridge_ops,
1333};
1334
1335UCLASS_DRIVER(pci_generic) = {
1336 .id = UCLASS_PCI_GENERIC,
1337 .name = "pci_generic",
1338};
1339
1340static const struct udevice_id pci_generic_ids[] = {
1341 { .compatible = "pci-generic" },
1342 { }
1343};
1344
1345U_BOOT_DRIVER(pci_generic_drv) = {
1346 .name = "pci_generic_drv",
1347 .id = UCLASS_PCI_GENERIC,
1348 .of_match = pci_generic_ids,
1349};
Stephen Warrene578b922016-01-26 11:10:11 -07001350
1351void pci_init(void)
1352{
1353 struct udevice *bus;
1354
1355 /*
1356 * Enumerate all known controller devices. Enumeration has the side-
1357 * effect of probing them, so PCIe devices will be enumerated too.
1358 */
1359 for (uclass_first_device(UCLASS_PCI, &bus);
1360 bus;
1361 uclass_next_device(&bus)) {
1362 ;
1363 }
1364}