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wdenk42d1f032003-10-15 23:53:47 +00001/*
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +08002 * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
Kumar Gala39aaca12009-03-19 02:46:19 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <ppc_asm.tmpl>
31#include <asm/processor.h>
Trent Piephoada591d2008-12-03 15:16:37 -080032#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000033
Wolfgang Denkd87080b2006-03-31 18:32:53 +020034DECLARE_GLOBAL_DATA_PTR;
35
wdenk42d1f032003-10-15 23:53:47 +000036/* --------------------------------------------------------------- */
37
wdenk42d1f032003-10-15 23:53:47 +000038void get_sys_info (sys_info_t * sysInfo)
39{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala39aaca12009-03-19 02:46:19 -050041#ifdef CONFIG_FSL_CORENET
42 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
43
44 const u8 core_cplx_PLL[16] = {
45 [ 0] = 0, /* CC1 PPL / 1 */
46 [ 1] = 0, /* CC1 PPL / 2 */
47 [ 2] = 0, /* CC1 PPL / 4 */
48 [ 4] = 1, /* CC2 PPL / 1 */
49 [ 5] = 1, /* CC2 PPL / 2 */
50 [ 6] = 1, /* CC2 PPL / 4 */
51 [ 8] = 2, /* CC3 PPL / 1 */
52 [ 9] = 2, /* CC3 PPL / 2 */
53 [10] = 2, /* CC3 PPL / 4 */
54 [12] = 3, /* CC4 PPL / 1 */
55 [13] = 3, /* CC4 PPL / 2 */
56 [14] = 3, /* CC4 PPL / 4 */
57 };
58
59 const u8 core_cplx_PLL_div[16] = {
60 [ 0] = 1, /* CC1 PPL / 1 */
61 [ 1] = 2, /* CC1 PPL / 2 */
62 [ 2] = 4, /* CC1 PPL / 4 */
63 [ 4] = 1, /* CC2 PPL / 1 */
64 [ 5] = 2, /* CC2 PPL / 2 */
65 [ 6] = 4, /* CC2 PPL / 4 */
66 [ 8] = 1, /* CC3 PPL / 1 */
67 [ 9] = 2, /* CC3 PPL / 2 */
68 [10] = 4, /* CC3 PPL / 4 */
69 [12] = 1, /* CC4 PPL / 1 */
70 [13] = 2, /* CC4 PPL / 2 */
71 [14] = 4, /* CC4 PPL / 4 */
72 };
73 uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080074 uint ratio[4];
Kumar Gala39aaca12009-03-19 02:46:19 -050075 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080076 uint mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -050077
78 sysInfo->freqSystemBus = sysclk;
79 sysInfo->freqDDRBus = sysclk;
Kumar Gala39aaca12009-03-19 02:46:19 -050080
James Yang93cedc72010-01-12 15:50:18 -060081 sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080082 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
83 if (mem_pll_rat > 2)
84 sysInfo->freqDDRBus *= mem_pll_rat;
85 else
86 sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -050087
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080088 ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
89 ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
90 ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
91 ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
92 for (i = 0; i < 4; i++) {
93 if (ratio[i] > 4)
94 freqCC_PLL[i] = sysclk * ratio[i];
95 else
96 freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
97 }
Kumar Gala39aaca12009-03-19 02:46:19 -050098 rcw_tmp = in_be32(&gur->rcwsr[3]);
99 for (i = 0; i < cpu_numcores(); i++) {
100 u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
101 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
102
103 sysInfo->freqProcessor[i] =
104 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
105 }
106
107#define PME_CLK_SEL 0x80000000
108#define FM1_CLK_SEL 0x40000000
109#define FM2_CLK_SEL 0x20000000
110 rcw_tmp = in_be32(&gur->rcwsr[7]);
111
112#ifdef CONFIG_SYS_DPAA_PME
113 if (rcw_tmp & PME_CLK_SEL)
Kumar Galabc20f9a2009-12-09 17:28:17 -0600114 sysInfo->freqPME = freqCC_PLL[2] / 2;
Kumar Gala693416f2010-01-25 11:01:51 -0600115 else
116 sysInfo->freqPME = sysInfo->freqSystemBus / 2;
Kumar Gala39aaca12009-03-19 02:46:19 -0500117#endif
118
119#ifdef CONFIG_SYS_DPAA_FMAN
120 if (rcw_tmp & FM1_CLK_SEL)
Kumar Galabc20f9a2009-12-09 17:28:17 -0600121 sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
Kumar Gala693416f2010-01-25 11:01:51 -0600122 else
123 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
Kumar Gala39aaca12009-03-19 02:46:19 -0500124#if (CONFIG_SYS_NUM_FMAN) == 2
125 if (rcw_tmp & FM2_CLK_SEL)
Kumar Galabc20f9a2009-12-09 17:28:17 -0600126 sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
Kumar Gala693416f2010-01-25 11:01:51 -0600127 else
128 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
Kumar Gala39aaca12009-03-19 02:46:19 -0500129#endif
130#endif
131
132#else
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500133 uint plat_ratio,e500_ratio,half_freqSystemBus;
Trent Piephoada591d2008-12-03 15:16:37 -0800134 uint lcrr_div;
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500135 int i;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400136#ifdef CONFIG_QE
137 u32 qe_ratio;
138#endif
wdenk42d1f032003-10-15 23:53:47 +0000139
140 plat_ratio = (gur->porpllsr) & 0x0000003e;
141 plat_ratio >>= 1;
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500142 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500143
144 /* Divide before multiply to avoid integer
145 * overflow for processor speeds above 2GHz */
146 half_freqSystemBus = sysInfo->freqSystemBus/2;
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530147 for (i = 0; i < cpu_numcores(); i++) {
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500148 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
149 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
150 }
James Yanga3e77fa2008-02-08 18:05:08 -0600151
152 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
Kumar Galad4357932007-12-07 04:59:26 -0600153 sysInfo->freqDDRBus = sysInfo->freqSystemBus;
154
155#ifdef CONFIG_DDR_CLK_FREQ
156 {
Jason Jinc0391112008-09-27 14:40:57 +0800157 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
158 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Galad4357932007-12-07 04:59:26 -0600159 if (ddr_ratio != 0x7)
160 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
161 }
162#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500163#endif
Trent Piephoada591d2008-12-03 15:16:37 -0800164
Haiying Wangb3d7f202009-05-20 12:30:29 -0400165#ifdef CONFIG_QE
166 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
167 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
168 sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
169#endif
170
Trent Piephoada591d2008-12-03 15:16:37 -0800171#if defined(CONFIG_SYS_LBC_LCRR)
172 /* We will program LCRR to this value later */
173 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
174#else
Becky Brucef51cdaf2010-06-17 11:37:20 -0500175 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
Trent Piephoada591d2008-12-03 15:16:37 -0800176#endif
177 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
Dave Liu0fd2fa62009-11-17 20:49:05 +0800178#if defined(CONFIG_FSL_CORENET)
179 /* If this is corenet based SoC, bit-representation
180 * for four times the clock divider values.
181 */
182 lcrr_div *= 4;
183#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
Trent Piephoada591d2008-12-03 15:16:37 -0800184 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
185 /*
186 * Yes, the entire PQ38 family use the same
187 * bit-representation for twice the clock divider values.
188 */
189 lcrr_div *= 2;
190#endif
191 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
192 } else {
193 /* In case anyone cares what the unknown value is */
194 sysInfo->freqLocalBus = lcrr_div;
195 }
wdenk42d1f032003-10-15 23:53:47 +0000196}
197
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500198
wdenk42d1f032003-10-15 23:53:47 +0000199int get_clocks (void)
200{
wdenk42d1f032003-10-15 23:53:47 +0000201 sys_info_t sys_info;
Timur Tabi88353a92008-04-04 11:15:58 -0500202#ifdef CONFIG_MPC8544
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
Timur Tabi88353a92008-04-04 11:15:58 -0500204#endif
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500205#if defined(CONFIG_CPM2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000207 uint sccr, dfbrg;
208
209 /* set VCO = 4 * BRG */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600210 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
211 sccr = cpm->im_cpm_intctl.sccr;
wdenk42d1f032003-10-15 23:53:47 +0000212 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
213#endif
214 get_sys_info (&sys_info);
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500215 gd->cpu_clk = sys_info.freqProcessor[0];
wdenk42d1f032003-10-15 23:53:47 +0000216 gd->bus_clk = sys_info.freqSystemBus;
James Yanga3e77fa2008-02-08 18:05:08 -0600217 gd->mem_clk = sys_info.freqDDRBus;
Trent Piephoada591d2008-12-03 15:16:37 -0800218 gd->lbc_clk = sys_info.freqLocalBus;
Timur Tabi88353a92008-04-04 11:15:58 -0500219
Haiying Wangb3d7f202009-05-20 12:30:29 -0400220#ifdef CONFIG_QE
221 gd->qe_clk = sys_info.freqQE;
222 gd->brg_clk = gd->qe_clk / 2;
223#endif
Timur Tabi88353a92008-04-04 11:15:58 -0500224 /*
225 * The base clock for I2C depends on the actual SOC. Unfortunately,
226 * there is no pattern that can be used to determine the frequency, so
227 * the only choice is to look up the actual SOC number and use the value
228 * for that SOC. This information is taken from application note
229 * AN2919.
230 */
231#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
232 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
Timur Tabi943afa22008-01-09 14:35:26 -0600233 gd->i2c1_clk = sys_info.freqSystemBus;
Timur Tabi88353a92008-04-04 11:15:58 -0500234#elif defined(CONFIG_MPC8544)
235 /*
236 * On the 8544, the I2C clock is the same as the SEC clock. This can be
237 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
238 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
239 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
240 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
241 */
242 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
Wolfgang Grandeggerdffd2442008-09-30 10:55:57 +0200243 gd->i2c1_clk = sys_info.freqSystemBus / 3;
Kumar Gala42653b82008-10-16 21:58:49 -0500244 else
245 gd->i2c1_clk = sys_info.freqSystemBus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500246#else
247 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
248 gd->i2c1_clk = sys_info.freqSystemBus / 2;
249#endif
250 gd->i2c2_clk = gd->i2c1_clk;
Timur Tabi943afa22008-01-09 14:35:26 -0600251
Dipen Dudhat6b9ea082009-09-01 17:27:00 +0530252#if defined(CONFIG_FSL_ESDHC)
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400253#ifdef CONFIG_MPC8569
254 gd->sdhc_clk = gd->bus_clk;
255#else
Kumar Galaef50d6c2008-08-12 11:14:19 -0500256 gd->sdhc_clk = gd->bus_clk / 2;
257#endif
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400258#endif /* defined(CONFIG_FSL_ESDHC) */
Kumar Galaef50d6c2008-08-12 11:14:19 -0500259
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500260#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +0000261 gd->vco_out = 2*sys_info.freqSystemBus;
262 gd->cpm_clk = gd->vco_out / 2;
263 gd->scc_clk = gd->vco_out / 4;
264 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
265#endif
266
267 if(gd->cpu_clk != 0) return (0);
268 else return (1);
269}
270
271
272/********************************************
273 * get_bus_freq
274 * return system bus freq in Hz
275 *********************************************/
276ulong get_bus_freq (ulong dummy)
277{
James Yanga3e77fa2008-02-08 18:05:08 -0600278 return gd->bus_clk;
wdenk42d1f032003-10-15 23:53:47 +0000279}
Kumar Galad4357932007-12-07 04:59:26 -0600280
281/********************************************
282 * get_ddr_freq
283 * return ddr bus freq in Hz
284 *********************************************/
285ulong get_ddr_freq (ulong dummy)
286{
James Yanga3e77fa2008-02-08 18:05:08 -0600287 return gd->mem_clk;
Kumar Galad4357932007-12-07 04:59:26 -0600288}