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wdenkc6097192002-11-03 00:24:07 +00001/*****************************************************************************/
2/* I2C Bus interface initialisation and I2C Commands */
3/* for PPC405GP */
4/* Author : AS HARNOIS */
5/* Date : 13.Dec.00 */
6/*****************************************************************************/
7
8#include <common.h>
9#include <ppc4xx.h>
10#if defined(CONFIG_440)
11# include <440_i2c.h>
12#else
13# include <405gp_i2c.h>
14#endif
15#include <i2c.h>
16
17#ifdef CONFIG_HARD_I2C
18
19#define IIC_OK 0
20#define IIC_NOK 1
21#define IIC_NOK_LA 2 /* Lost arbitration */
22#define IIC_NOK_ICT 3 /* Incomplete transfer */
23#define IIC_NOK_XFRA 4 /* Transfer aborted */
24#define IIC_NOK_DATA 5 /* No data in buffer */
25#define IIC_NOK_TOUT 6 /* Transfer timeout */
26
27#define IIC_TIMEOUT 1 /* 1 seconde */
28
29
30static void _i2c_bus_reset (void)
31{
32 int i, status;
33
34 /* Reset status register */
35 /* write 1 in SCMP and IRQA to clear these fields */
36 out8 (IIC_STS, 0x0A);
37
38 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
39 out8 (IIC_EXTSTS, 0x8F);
40 __asm__ volatile ("eieio");
41
42 /*
43 * Get current state, reset bus
44 * only if no transfers are pending.
45 */
46 i = 10;
47 do {
48 /* Get status */
49 status = in8 (IIC_STS);
50 udelay (500); /* 500us */
51 i--;
52 } while ((status & IIC_STS_PT) && (i > 0));
53 /* Soft reset controller */
54 status = in8 (IIC_XTCNTLSS);
55 out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST));
56 __asm__ volatile ("eieio");
57
58 /* make sure where in initial state, data hi, clock hi */
59 out8 (IIC_DIRECTCNTL, 0xC);
60 for (i = 0; i < 10; i++) {
61 if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
62 /* clock until we get to known state */
63 out8 (IIC_DIRECTCNTL, 0x8); /* clock lo */
64 udelay (100); /* 100us */
65 out8 (IIC_DIRECTCNTL, 0xC); /* clock hi */
66 udelay (100); /* 100us */
67 } else {
68 break;
69 }
70 }
71 /* send start condition */
72 out8 (IIC_DIRECTCNTL, 0x4);
73 udelay (1000); /* 1ms */
74 /* send stop condition */
75 out8 (IIC_DIRECTCNTL, 0xC);
76 udelay (1000); /* 1ms */
77 /* Unreset controller */
78 out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
79 udelay (1000); /* 1ms */
80}
81
82void i2c_init (int speed, int slaveadd)
83{
84 sys_info_t sysInfo;
85 unsigned long freqOPB;
86 int val, divisor;
87
wdenk8bde7f72003-06-27 21:31:46 +000088#ifdef CFG_I2C_INIT_BOARD
wdenk47cd00f2003-03-06 13:39:27 +000089 /* call board specific i2c bus reset routine before accessing the */
90 /* environment, which might be in a chip on that bus. For details */
91 /* about this problem see doc/I2C_Edge_Conditions. */
92 i2c_init_board();
93#endif
94
wdenkc6097192002-11-03 00:24:07 +000095 /* Handle possible failed I2C state */
wdenk47cd00f2003-03-06 13:39:27 +000096 /* FIXME: put this into i2c_init_board()? */
wdenkc6097192002-11-03 00:24:07 +000097 _i2c_bus_reset ();
98
99 /* clear lo master address */
100 out8 (IIC_LMADR, 0);
101
102 /* clear hi master address */
103 out8 (IIC_HMADR, 0);
104
105 /* clear lo slave address */
106 out8 (IIC_LSADR, 0);
107
108 /* clear hi slave address */
109 out8 (IIC_HSADR, 0);
110
111 /* Clock divide Register */
112 /* get OPB frequency */
113 get_sys_info (&sysInfo);
114 freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
115 /* set divisor according to freqOPB */
116 divisor = (freqOPB - 1) / 10000000;
117 if (divisor == 0)
118 divisor = 1;
119 out8 (IIC_CLKDIV, divisor);
120
121 /* no interrupts */
122 out8 (IIC_INTRMSK, 0);
123
124 /* clear transfer count */
125 out8 (IIC_XFRCNT, 0);
126
127 /* clear extended control & stat */
128 /* write 1 in SRC SRS SWC SWS to clear these fields */
129 out8 (IIC_XTCNTLSS, 0xF0);
130
131 /* Mode Control Register
132 Flush Slave/Master data buffer */
133 out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
134 __asm__ volatile ("eieio");
135
136
wdenk8bde7f72003-06-27 21:31:46 +0000137 val = in8(IIC_MDCNTL);
138 __asm__ volatile ("eieio");
wdenkc6097192002-11-03 00:24:07 +0000139
wdenk8bde7f72003-06-27 21:31:46 +0000140 /* Ignore General Call, slave transfers are ignored,
141 disable interrupts, exit unknown bus state, enable hold
142 SCL
143 100kHz normaly or FastMode for 400kHz and above
144 */
wdenkc6097192002-11-03 00:24:07 +0000145
wdenk8bde7f72003-06-27 21:31:46 +0000146 val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
147 if( speed >= 400000 ){
148 val |= IIC_MDCNTL_FSM;
149 }
wdenkc6097192002-11-03 00:24:07 +0000150 out8 (IIC_MDCNTL, val);
151
152 /* clear control reg */
153 out8 (IIC_CNTL, 0x00);
154 __asm__ volatile ("eieio");
155
156}
157
158/*
159 This code tries to use the features of the 405GP i2c
160 controller. It will transfer up to 4 bytes in one pass
161 on the loop. It only does out8(lbz) to the buffer when it
162 is possible to do out16(lhz) transfers.
163
164 cmd_type is 0 for write 1 for read.
165
166 addr_len can take any value from 0-255, it is only limited
167 by the char, we could make it larger if needed. If it is
168 0 we skip the address write cycle.
169
170 Typical case is a Write of an addr followd by a Read. The
171 IBM FAQ does not cover this. On the last byte of the write
172 we don't set the creg CHT bit, and on the first bytes of the
173 read we set the RPST bit.
174
175 It does not support address only transfers, there must be
176 a data part. If you want to write the address yourself, put
177 it in the data pointer.
178
179 It does not support transfer to/from address 0.
180
181 It does not check XFRCNT.
182*/
183static
184int i2c_transfer(unsigned char cmd_type,
wdenk8bde7f72003-06-27 21:31:46 +0000185 unsigned char chip,
186 unsigned char addr[],
187 unsigned char addr_len,
188 unsigned char data[],
wdenkc6097192002-11-03 00:24:07 +0000189 unsigned short data_len )
190{
wdenk8bde7f72003-06-27 21:31:46 +0000191 unsigned char* ptr;
192 int reading;
193 int tran,cnt;
194 int result;
195 int status;
196 int i;
197 uchar creg;
wdenkc6097192002-11-03 00:24:07 +0000198
wdenk8bde7f72003-06-27 21:31:46 +0000199 if( data == 0 || data_len == 0 ){
200 /*Don't support data transfer of no length or to address 0*/
201 printf( "i2c_transfer: bad call\n" );
202 return IIC_NOK;
203 }
204 if( addr && addr_len ){
205 ptr = addr;
206 cnt = addr_len;
207 reading = 0;
208 }else{
209 ptr = data;
210 cnt = data_len;
211 reading = cmd_type;
212 }
wdenkc6097192002-11-03 00:24:07 +0000213
wdenk8bde7f72003-06-27 21:31:46 +0000214 /*Clear Stop Complete Bit*/
215 out8(IIC_STS,IIC_STS_SCMP);
216 /* Check init */
217 i=10;
218 do {
219 /* Get status */
220 status = in8(IIC_STS);
221 __asm__ volatile("eieio");
222 i--;
223 } while ((status & IIC_STS_PT) && (i>0));
wdenkc6097192002-11-03 00:24:07 +0000224
wdenk8bde7f72003-06-27 21:31:46 +0000225 if (status & IIC_STS_PT) {
226 result = IIC_NOK_TOUT;
227 return(result);
228 }
229 /*flush the Master/Slave Databuffers*/
230 out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
231 /*need to wait 4 OPB clocks? code below should take that long*/
wdenkc6097192002-11-03 00:24:07 +0000232
wdenk8bde7f72003-06-27 21:31:46 +0000233 /* 7-bit adressing */
234 out8(IIC_HMADR,0);
235 out8(IIC_LMADR, chip);
236 __asm__ volatile("eieio");
wdenkc6097192002-11-03 00:24:07 +0000237
wdenk8bde7f72003-06-27 21:31:46 +0000238 tran = 0;
239 result = IIC_OK;
240 creg = 0;
wdenkc6097192002-11-03 00:24:07 +0000241
wdenk8bde7f72003-06-27 21:31:46 +0000242 while ( tran != cnt && (result == IIC_OK)) {
243 int bc,j;
wdenkc6097192002-11-03 00:24:07 +0000244
wdenk8bde7f72003-06-27 21:31:46 +0000245 /* Control register =
246 Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
247 Transfer is a sequence of transfers
wdenkc6097192002-11-03 00:24:07 +0000248 */
wdenk8bde7f72003-06-27 21:31:46 +0000249 creg |= IIC_CNTL_PT;
250
251 bc = (cnt - tran) > 4 ? 4 :
252 cnt - tran;
253 creg |= (bc-1)<<4;
254 /* if the real cmd type is write continue trans*/
255 if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
256 creg |= IIC_CNTL_CHT;
257
258 if (reading)
259 creg |= IIC_CNTL_READ;
260 else {
261 for(j=0; j<bc; j++) {
262 /* Set buffer */
263 out8(IIC_MDBUF,ptr[tran+j]);
264 __asm__ volatile("eieio");
265 }
266 }
267 out8(IIC_CNTL, creg );
268 __asm__ volatile("eieio");
269
270 /* Transfer is in progress
271 we have to wait for upto 5 bytes of data
272 1 byte chip address+r/w bit then bc bytes
273 of data.
274 udelay(10) is 1 bit time at 100khz
275 Doubled for slop. 20 is too small.
276 */
277 i=2*5*8;
278 do {
279 /* Get status */
280 status = in8(IIC_STS);
281 __asm__ volatile("eieio");
282 udelay (10);
283 i--;
284 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
wdenkc6097192002-11-03 00:24:07 +0000285 && (i>0));
286
wdenk8bde7f72003-06-27 21:31:46 +0000287 if (status & IIC_STS_ERR) {
288 result = IIC_NOK;
289 status = in8 (IIC_EXTSTS);
290 /* Lost arbitration? */
291 if (status & IIC_EXTSTS_LA)
292 result = IIC_NOK_LA;
293 /* Incomplete transfer? */
294 if (status & IIC_EXTSTS_ICT)
295 result = IIC_NOK_ICT;
296 /* Transfer aborted? */
297 if (status & IIC_EXTSTS_XFRA)
298 result = IIC_NOK_XFRA;
299 } else if ( status & IIC_STS_PT) {
300 result = IIC_NOK_TOUT;
301 }
302 /* Command is reading => get buffer */
303 if ((reading) && (result == IIC_OK)) {
304 /* Are there data in buffer */
305 if (status & IIC_STS_MDBS) {
306 /*
307 even if we have data we have to wait 4OPB clocks
308 for it to hit the front of the FIFO, after that
309 we can just read. We should check XFCNT here and
310 if the FIFO is full there is no need to wait.
wdenkc6097192002-11-03 00:24:07 +0000311 */
wdenk8bde7f72003-06-27 21:31:46 +0000312 udelay (1);
313 for(j=0;j<bc;j++) {
314 ptr[tran+j] = in8(IIC_MDBUF);
315 __asm__ volatile("eieio");
316 }
317 } else
318 result = IIC_NOK_DATA;
319 }
320 creg = 0;
321 tran+=bc;
322 if( ptr == addr && tran == cnt ) {
323 ptr = data;
324 cnt = data_len;
325 tran = 0;
326 reading = cmd_type;
327 if( reading )
328 creg = IIC_CNTL_RPST;
329 }
330 }
331 return (result);
wdenkc6097192002-11-03 00:24:07 +0000332}
333
334int i2c_probe (uchar chip)
335{
336 uchar buf[1];
337
338 buf[0] = 0;
339
wdenk8bde7f72003-06-27 21:31:46 +0000340 /*
341 * What is needed is to send the chip address and verify that the
342 * address was <ACK>ed (i.e. there was a chip at that address which
343 * drove the data line low).
344 */
345 return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
wdenkc6097192002-11-03 00:24:07 +0000346}
347
348
wdenkc6097192002-11-03 00:24:07 +0000349int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
350{
wdenk8bde7f72003-06-27 21:31:46 +0000351 uchar xaddr[4];
352 int ret;
wdenkc6097192002-11-03 00:24:07 +0000353
354 if ( alen > 4 ) {
355 printf ("I2C read: addr len %d not supported\n", alen);
356 return 1;
357 }
358
wdenk8bde7f72003-06-27 21:31:46 +0000359 if ( alen > 0 ) {
360 xaddr[0] = (addr >> 24) & 0xFF;
361 xaddr[1] = (addr >> 16) & 0xFF;
362 xaddr[2] = (addr >> 8) & 0xFF;
363 xaddr[3] = addr & 0xFF;
364 }
wdenkc6097192002-11-03 00:24:07 +0000365
366
367#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
368 /*
wdenk8bde7f72003-06-27 21:31:46 +0000369 * EEPROM chips that implement "address overflow" are ones
370 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
371 * address and the extra bits end up in the "chip address"
372 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
373 * four 256 byte chips.
wdenkc6097192002-11-03 00:24:07 +0000374 *
wdenk8bde7f72003-06-27 21:31:46 +0000375 * Note that we consider the length of the address field to
376 * still be one byte because the extra address bits are
377 * hidden in the chip address.
wdenkc6097192002-11-03 00:24:07 +0000378 */
wdenk8bde7f72003-06-27 21:31:46 +0000379 if( alen > 0 )
380 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
wdenkc6097192002-11-03 00:24:07 +0000381#endif
wdenk8bde7f72003-06-27 21:31:46 +0000382 if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
383 printf( "I2c read: failed %d\n", ret);
384 return 1;
385 }
386 return 0;
wdenkc6097192002-11-03 00:24:07 +0000387}
388
389int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
390{
wdenk8bde7f72003-06-27 21:31:46 +0000391 uchar xaddr[4];
wdenkc6097192002-11-03 00:24:07 +0000392
393 if ( alen > 4 ) {
394 printf ("I2C write: addr len %d not supported\n", alen);
395 return 1;
396
397 }
wdenk8bde7f72003-06-27 21:31:46 +0000398 if ( alen > 0 ) {
399 xaddr[0] = (addr >> 24) & 0xFF;
400 xaddr[1] = (addr >> 16) & 0xFF;
401 xaddr[2] = (addr >> 8) & 0xFF;
402 xaddr[3] = addr & 0xFF;
403 }
wdenkc6097192002-11-03 00:24:07 +0000404
405#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
406 /*
wdenk8bde7f72003-06-27 21:31:46 +0000407 * EEPROM chips that implement "address overflow" are ones
408 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
409 * address and the extra bits end up in the "chip address"
410 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
411 * four 256 byte chips.
wdenkc6097192002-11-03 00:24:07 +0000412 *
wdenk8bde7f72003-06-27 21:31:46 +0000413 * Note that we consider the length of the address field to
414 * still be one byte because the extra address bits are
415 * hidden in the chip address.
wdenkc6097192002-11-03 00:24:07 +0000416 */
wdenk8bde7f72003-06-27 21:31:46 +0000417 if( alen > 0 )
418 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
wdenkc6097192002-11-03 00:24:07 +0000419#endif
420
wdenk8bde7f72003-06-27 21:31:46 +0000421 return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
wdenkc6097192002-11-03 00:24:07 +0000422}
423
wdenk1cb8e982003-03-06 21:55:29 +0000424/*-----------------------------------------------------------------------
425 * Read a register
426 */
427uchar i2c_reg_read(uchar i2c_addr, uchar reg)
428{
429 char buf;
430
431 i2c_read(i2c_addr, reg, 1, &buf, 1);
432
433 return(buf);
434}
435
436/*-----------------------------------------------------------------------
437 * Write a register
438 */
439void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
440{
441 i2c_write(i2c_addr, reg, 1, &val, 1);
442}
wdenkc6097192002-11-03 00:24:07 +0000443#endif /* CONFIG_HARD_I2C */